A method and circuit write a memory cell. The method applies a pulse train to a write line connected to the memory cell. The number of pulses in the pulse train is not predetermined. The method compares a value on the input side of the cell to a reference value, wherein the input side of the memory cell provides an indication that a writing operation is complete. The method discontinues the pulse train on the write line, in response to the comparing step, preferably if the value on the write line exceeds the reference value. Preferably, the pulses are short in width and large in magnitude. The method may optionally count the number of pulses in the pulse train, and discontinue the pulse train on the write line and/or declare the cell as unusable if the number of pulses exceeds a predetermined maximum. The circuit comprises a pulse train generator and a comparator. The pulse train generator has an output and an enable input. The output is connected to a write line connected to the memory cell. The output, when enabled, carries a pulse train. The comparator has two inputs and an output. One of the inputs is connected to the write line. The other of the inputs is connected to a reference. The output is connected to the enable input of the pulse train generator, whereby the pulse train generator is disabled or enabled depending upon the comparator output. Optionally, the circuit further comprises a counter that counts pulses and disables the pulse train generator after a predetermined maximum number of pulses. A complete memory system comprises an array of memory cells, a write line, and a pulse train generator and comparator as described above.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for writing a memory cell, the method comprising: initiating a pulse train on a write line connected to the memory cell, wherein a plurality of pulses in the pulse train is not predetermined; comparing a reference value to a value on an input side of the memory cell, wherein the input side of the memory cell provides an indication that a writing operation is complete; and discontinuing the pulse train on the write line in response to the indication that the writing operation is complete.
2. The method of claim 1 , wherein the pulse train comprises the plurality of pulses that are substantially short in width and substantially large in magnitude.
3. The method of claim 1 wherein the memory cell comprises a fuse and an anti-fuse in series.
4. The method of claim 1 wherein the memory cell is selected from the group consisting of a bipolar PROM, a CMOS PROM, an EPROM, and a tunnel-junction anti-fuse.
5. The method of claim 1 wherein the reference value and the value on the input side of the cell are voltages.
6. The method of claim 1 wherein the value on the input side of the cell is a value on the write line.
7. The method of claim 1 wherein the discontinuing step further comprises: discontinuing the pulse train on the write line, if the value on the write line exceeds the reference value.
8. The method of claim 1 , further comprising: counting a number for the plurality of pulses in the pulse train on the write line.
9. The method of claim 8 , further comprising: discontinuing the pulse train on the write line in response to the number exceeding a predetermined maximum.
10. The method of claim 8 , further comprising: declaring the memory cell as unusable in response to the number exceeding a predetermined maximum.
11. The method of claim 8 further comprising: logging the number of pulses.
12. A circuit for writing a memory cell, the circuit comprising: a pulse train generator having an output and an enable input, the output connected to a write line connected to the memory cell, the output, when enabled, being a plurality of pulses in a pulse train; and a comparator having two inputs and a comparator output, one of the inputs connected to the write line, the other of the inputs connected to a reference, the comparator output connected to the enable input of the pulse train generator, wherein the pulse train generator is one of disabled and enabled based on the comparator output.
13. The circuit of claim 12 further comprising: a counter storing a count value, the counter having an output connected to the enable input of the pulse train generator, wherein the counter counts pulses and disables the pulse train generator after a predetermined maximum number of pulses.
14. The circuit of claim 13 further comprising: a logic gate having two inputs and an output, one of the inputs connected to the output of the comparator, the other of the outputs connected to the counter output, the logic gate output connected to the enable input of the pulse train generator.
15. The circuit of claim 12 further comprising: a controller connected to the counter.
16. The circuit of claim 12 further comprising: a voltage divider connected between the pulse train generator output and the write line, wherein an intermediate node in the voltage divider is connected to the comparator input.
17. The circuit of claim 12 further comprising: a transistor connected between the pulse train generator output and the write line, the comparator output being connected to a terminal of the transistor such that the transistor is conducting or non-conducting depending upon the comparator output.
18. The circuit of claim 12 wherein the pulse train generator comprises: an oscillator; and an OR gate having two inputs and an output, one of the inputs connected to the oscillator, the other of the inputs being the enable input, the OR gate output being the pulse train generator output.
19. A memory system comprising: an array of memory cells; a write line connectable to at least one of the memory cells in the array; a pulse train generator having an output and an enable input, the output connected to the write line, the output, when enabled, being a plurality of pulses in a pulse train; and a comparator having two inputs and an output, one of the inputs connected to the write line, the other of the inputs connected to a reference, the output connected to the enable input of the pulse train generator, whereby the pulse train generator is disabled or enabled depending upon the comparator output.
20. The memory system of claim 19 further comprising: a row decoder connected to the array; and a column decoder connected to the array.
21. A method for writing a memory cell, the method comprising: initiating a pulse train on a write line connected to the memory cell, wherein a number of pulses in the pulse train is not predetermined; comparing a reference value to a value on an input side of the memory cell, wherein the input side of the memory cell provides an indication that a writing operation is complete; discontinuing the pulse train on the write line in response to the indication that the writing operation is complete; and counting the number of pulses in the pulse train on the write line.
22. The method of claim 21 , further comprising: discontinuing the pulse train on the write line if the number of pulses exceeds a predetermined maximum.
23. The method of claim 21 , further comprising: declaring the cell as unusable if the number of pulses exceeds a predetermined maximum.
24. The method of claim 21 , further comprising: logging the number of pulses.
25. A circuit for writing a memory cell, the circuit comprising: a pulse train generator having an output and an enable input, the output connected to a write line connected to the memory cell, the output, when enabled, being a pulse train; a comparator having two inputs and an output, one of the inputs connected to the write line, the other of the inputs connected to a reference, the output connected to the enable input of the pulse train generator, whereby the pulse train generator is disabled or enabled depending upon the comparator output; and a counter storing a count value, the counter having an output connected to the enable input of the pulse train generator, wherein the counter counts pulses and disables the pulse train generator after a predetermined maximum number of pulses.
26. The circuit of claim 25 , further comprising: a logic gate having two inputs and an output, one of the inputs connected to the output of the comparator, the other of the outputs connected to the counter output, the logic gate output connected to the enable input of the pulse train generator.
27. A circuit for writing a memory cell, the circuit comprising: a pulse train generator having an output and an enable input, the output connected to a write line connected to the memory cell, the output, when enabled, being a pulse train; a comparator having two inputs and an output, one of the inputs connected to the write line, the other of the inputs connected to a reference, the output connected to the enable input of the pulse train generator, whereby the pulse train generator is disabled or enabled depending upon the comparator output; and a voltage divider connected between the pulse train generator output and the write line, wherein an intermediate node in the voltage divider is connected to the comparator input.
28. A circuit for writing a memory cell, the circuit comprising: a pulse train generator having an output and an enable input, the output connected to a write line connected to the memory cell, the output, when enabled, being a pulse train; wherein said pulse train generator comprises: an oscillator; and an AND gate having two inputs and an output, one of the inputs connected to the output of an S-R flip flop, the other of the inputs being the enable input, the AND gate output enable the connection of the pulse train generator output to the write line; and a comparator having two inputs and an output, one of the inputs connected to the write line, the other of the inputs connected to a reference, the output connected to a clock input of the S-R flip flop.
29. A circuit for writing a memory cell, the circuit comprising: a pulse train generator having an output and an enable input, the output connected to a write line connected to the memory cell, the output, when enabled, being a plurality of pulses in a pulse train; a comparator having two inputs and a comparator output, one of the inputs connected to the write line, the other of the inputs connected to a reference, an S-R flip-flop, wherein the comparator output is connected to a clock input of the S-R flip-flop; and a controller having an input connected to the comparator output and an output connected to the enable input of the pulse train generator, wherein the pulse train generator output is disconnected from the write line upon a change from a low voltage to a high voltage state on the comparator.
30. The circuit of claim 29 , further comprising: a counter storing a count value, the counter having a counter output connected to the enable input of the pulse train generator, wherein the counter counts pulses and disables the pulse train generator after a predetermined maximum number of pulses.
31. The circuit of claim 30 , further comprising: a logic gate having two logic gate inputs and a logic gate output, a first logic gate input connected to the comparator, the second logic gate input connected to the counter output, the logic gate output connected to the gate input of a transistor that enable or disable the connection of pulse generator output to the write line.
32. The circuit of claim 29 , further comprising: a controller connected to the counter.
33. The circuit of claim 29 , further comprising: a voltage divider connected between the pulse train generator output and the write line, wherein an intermediate node in the voltage divider is connected to the comparator input.
34. The circuit of claim 29 , further comprising: a transistor connected between the pulse train generator output and the write line, the comparator output being connected to a terminal of the transistor such that the transistor is conducting or non-conducting depending upon the comparator output.
35. The circuit of claim 29 , wherein the pulse train generator comprises: an oscillator; and an AND gate having two inputs and an output, one of the inputs connected to the output of S-R flip flop, the other of the inputs being the enable input, the AND gate output being the enable control to the pulse train generator output.
36. A memory system comprising: an array of memory cells; a write line connectable to at least one of the memory cells in the array; a pulse train generator having an output and an enable input, the output connected to the write line, the output, when enabled, being a plurality of pulses in a pulse train; and a comparator having two inputs and an output, one of the inputs connected to the write line, the other of the inputs connected to a reference, a S-R flip-flop, wherein the comparator output is connected to a clock input of the S-R flip-flop; and a controller having an input connected to the comparator output and an output connected to the enable input of the pulse train generator, wherein the pulse train generator output is disconnected from the write line upon a change from a low voltage to a high voltage state on the comparator.
37. The memory system of claim 36 , further comprising: a row decoder connected to the array; and a column decoder connected to the array.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 20, 2001
August 13, 2002
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