A method for removing surface oxide from polysilicon includes depositing a very thin layer of germanium (e.g. monolayers in thickness) over the polysilicon immediately before a subsequent polysilicon deposition step, and then heating the germanium-coated polysilicon in a vacuum to sublime (remove) volatile germanium oxide. This method is applied to formation of a trench capacitor, which uses either doped amorphous silicon or doped amorphous SiGe material in the formation of the electrodes.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for removing surface oxide from polysilicon, comprising: providing a first polysilicon layer having a surface oxide layer; depositing a barrier layer on the surface oxide layer; baking the first polysilicon, surface oxide, and barrier layers until the barrier layer reacts with the surface oxide layer to form a volatile sub-oxide layer; and subliming the sub-oxide layer away to leave the first polysilicon layer with an oxide-free surface.
2. The method of claim 1 , wherein the barrier layer includes at least one layer of germanium.
3. The method of claim 1 , further comprising: depositing a second polysilicon layer on the oxide-free surface of the first polysilicon layer.
4. A method for forming a trench capacitor, comprising: forming a trench in a substrate; filling a portion of said trench with a first polysilicon layer, said first polysilicon layer having a surface oxide layer; depositing a barrier layer on the surface oxide layer; baking said first polysilicon, surface oxide, and barrier layers until said barrier layer reacts with said surface oxide layer to form a volatile sub-oxide layer; and subliming the sub-oxide layer away to leave said first polysilicon layer with an oxide-free surface.
5. The method of claim 4 , wherein said barrier layer includes germanium.
6. The method of claim 4 , further comprising: depositing a second polysilicon layer on the oxide-free surface of said first polysilicon layer within said trench, said second polysilicon layer having a surface oxide layer.
7. The method of claim 6 , further comprising: depositing a barrier layer on the surface oxide layer of said second polysilicon layer; baking said second polysilicon, surface oxide, and barrier layers until said barrier layer reacts with said surface oxide layer to form a volatile sub-oxide layer; and subliming the sub-oxide layer away to leave said second polysilicon layer with an oxide-free surface.
8. The method of claim 7 wherein the barrier layer deposited on the surface oxide layer of said second polysilicon layer includes germanium.
9. The method of claim 7 , further comprising: depositing a third polysilicon layer on the oxide-free surface of said second polysilicon layer.
10. The method of claim 4 , wherein said first polysilicon layer is an arsenic-doped amorphous silicon layer.
11. The method of claim 6 , wherein said second polysilicon layer is an arsenic-doped amorphous silicon layer.
12. The method of claim 9 , wherein said third polysilicon layer is an arsenic-doped amorphous silicon layer.
13. The method of claim 4 , wherein said first polysilicon layer is an arsenic-doped amorphous SiGe layer.
14. The method of claim 6 , wherein said second polysilicon layer is an arsenic-doped amorphous SiGe layer.
15. The method of claim 9 , wherein said third polysilicon layer is an arsenic-doped amorphous SiGe layer.
16. A trench capacitor, comprising: a first deposited silicon layer formed in a trench etched into a semiconductor substrate; and a second deposited silicon layer formed on said first deposited silicon layer after removal of a native oxide formed on said first deposited silicon layer by reaction with a barrier layer deposited thereon to form a sub-oxide thereof and sublimation away of said sub-oxide, such that an interface between said first deposited silicon layer and said second deposited silicon layer in said trench is an oxide-free interface.
17. The trench capacitor of claim 16 , wherein said first deposited silicon layer and said second deposited silicon layer are ones selected from a group consisting of amorphous silicon and amorphous SiGe.
18. The trench capacitor of claim 16 , further comprising: a third deposited silicon layer formed on said second deposited silicon layer after removal of a native oxide formed on said second deposited silicon layer by reaction with a barrier layer deposited thereon to form a sub-oxide thereof and sublimation away of said sub-oxide, such that an interface between said second deposited silicon layer and said third deposited silicon layer in said trench is an oxide-free interface.
19. The trench capacitor of claim 18 , wherein said third deposited silicon layer is one of amorphous silicon and amorphous SiGe.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 19, 2001
August 20, 2002
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