The present invention increases data transfer rate and reduces interrupt latency while avoiding a concomitant increase in interrupts to the host, by pacing the data flow between the UART and DSP using burst modes and wait modes.
Legal claims defining the scope of protection, as filed with the USPTO.
1. In a digital communication device with a parallel interface connectable to a host bus of a host computer and a DSP bus connected to a DSP of the modem, a receive channel including a receive write buffer connected to the DSP bus and a receive read buffer connected to the parallel interface, a transmit channel including a transmit read buffer connected to the DSP bus and a transmit write buffer connected to the parallel interface, a method of pacing data transfer comprising: in the transmit channel: entering a burst mode by enabling the transmit write buffer to write data to the transmit read buffer while enabling the transmit read buffer to read data from the transmit write buffer for a period of time corresponding to a first burst duration; and upon the expiration of the first burst duration, entering a first wait mode by inhibiting the transmit read and write buffers from reading and writing, respectively, for a first predetermined period of time corresponding to a first wait duration, wherein the first predetermined period of time is determined in accordance with a first predetermined value stored in a first pacing wait register.
2. The method of claim 1 further comprising: during the first burst duration, permitting a limited number N of interrupts to be asserted to the host computer; during the first wait duration, inhibiting interrupts to the host computer.
3. The method of claim 2 further comprising: during the first burst duration, inhibiting interrupts to the host computer after the assertion of N interrupts.
4. The method of claim 2 wherein N 1.
5. The method of claim 1 wherein the step of entering the burst mode is preceded by determining whether data is available in the transmit write buffer, wherein the step of entering the burst mode is postponed until data is available in the transmit write buffer.
6. The method of claim 1 wherein the step of determining whether data is available from the transmit write buffer is performed after the expiration of the first wait duration.
7. The method of claim 1 further comprising: in the receive channel: entering a burst mode by enabling the receive write buffer to write data to the receive read buffer while enabling the receive read buffer to read data for a period of time corresponding to a second burst duration; and upon the expiration of the second burst duration, entering a second wait mode by inhibiting the receive read and write buffers from reading and writing, respectively, for a second predetermined period of time corresponding to a second wait duration, wherein the second predetermined period of time is determined in accordance with a second predetermined value stored in a second pacing wait register.
8. The method of claim 7 wherein, in the receive channel, the step of entering a burst mode is preceded by: waiting until the receive read buffer contents exceeds a threshold and then asserting an interrupt to the host computer.
9. The method of claim 8 wherein, in the receive channel, the step of waiting is followed by a step of waiting until at least some data from the receive read buffer has been removed before performing the step of entering a burst mode.
10. The method of claim 9 further comprising waiting until data is available from the receive write buffer before performing the step of asserting an interrupt to the host.
11. In a digital communication device with a parallel interface connectable to a host bus of a host computer and a DSP bus connected to a DSP of the modem, a receive channel including a receive write buffer connected to the DSP bus and a receive read buffer connected to the parallel interface, a transmit channel including a transmit read buffer connected to the DSP bus and a transmit write buffer connected to the parallel interface, a method of pacing data transfer comprising: in the receive channel: entering a burst mode by enabling the receive write buffer to write data to the receive read buffer while enabling the receive read buffer to read data from the receive write buffer for a period of time corresponding to a burst duration; and upon the expiration of the burst duration, entering a wait mode by inhibiting the receive read and write buffers from reading and writing, respectively, for a predetermined period of time corresponding to a wait duration, wherein the predetermined period of time is determined in accordance with a predetermined value stored in a pacing wait register.
12. The method of claim 11 wherein, in the receive channel, the step of entering a burst mode is preceded by: waiting until the receive read buffer contents exceeds a threshold and then asserting an interrupt to the host computer.
13. The method of claim 12 wherein, in the receive channel, the step of waiting is followed by a step of waiting until at least some data from the receive read buffer has been removed before performing the step of entering a burst mode.
14. The method of claim 13 further comprising waiting until data is available from the receive write buffer before performing the step of asserting an interrupt to the host.
15. In a digital communication device with a parallel interface connectable to a host bus of a host computer and a DSP bus connected to a DSP of the modem, a receive channel including a receive write buffer connected to the DSP bus and a receive read buffer connected to the parallel interface, said receive read and write buffers being connected together, a transmit channel including a transmit read buffer connected to the DSP bus and a transmit write buffer connected to the parallel interface, said transmit read and write buffers being connected together, data transfer pacing circuitry comprising: a receive data transfer controller having a read signal output connected to said receive read buffer and a write signal output connected to said receive write buffer, said receive data transfer controller asserting said read and write signal outputs during a burst mode of a first duration and refraining from asserting said read and write signal outputs during a wait mode of a second duration; and a transmit data transfer controller having a transmit read signal output connected to said transmit read buffer and a transmit write signal output connected to said transmit write buffer, said transmit data transfer controller asserting said transmit read and write signal outputs during a burst mode of a third duration and refraining from asserting said transmit read and write signal outputs during a wait mode of a fourth duration.
16. The apparatus of claim 15 wherein said first and third durations are the same and said second and fourth durations are the same.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 28, 1999
August 20, 2002
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.