Digital signal processor and digital signal processing method

1. A digital signal processor comprising: a storage device that stores plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing; a counter that updates a count value thereof every sampling period and generates the updated count value as a basic address; and a sampled data input and output device that performs an input and output operation every sampling period, the input and output operation comprising generating plural kinds of offset addresses corresponding, respectively, to the plural kinds of signal processing and not overlapping with each other, generating at least one write address or read address for the sampled data for each of the plural kinds of signal processing by modifying the basic address by at least one of the offset addresses corresponding to each of the plural kinds of signal processing, and delivering the generated at least one write address or read address to the storage device.

2. A digital signal processor as claimed in claim 1 , wherein said plural kinds of signal processing include at least one kind of signal processing which includes a process of storing a plurality of sampled data in said storage device or reading a plurality of sampled data from said storage device every sampling period, said sampled data input and output device performing said input and output operation every sampling period, the input and output operation comprising generating a plurality of offset addresses corresponding to said at least one kind of signal processing, generating a plurality of write addresses or read addresses for the sampled data for the at least one kind of signal processing by modifying the basic address by the plurality of offset addresses, and delivering the generated plurality of write addresses or read addresses to the storage device.

3. A digital signal processor as claimed in claim 1 , wherein said plural kinds of signal processing include 1/M-fold decimation processing which includes a process of storing M pieces of sampled data (M is an integer) in said storage device and reading one piece of sampled data from said storage device every sampling period, said sampled data input and output device performing an input and output operation every sampling period, the input and output operation comprising generating M offset addresses for writing corresponding to said 1/M-fold decimation processing, generating M write addresses which differ from each other by modifying the basic address by the M offset addresses for writing, delivering the generated M write addresses to the storage device, generating one offset address for reading corresponding to said 1/M-fold decimation processing, generating one read address by modifying the basic address by the one offset address for reading, and delivering the generated one read address to the storage device.

4. A digital signal processor as claimed in claim 1 , wherein said plural kinds of signal processing include K-times oversampling processing which includes a process of storing one piece of sampled data in said storage device and reading J pieces of sampled data (J is an integer) from said storage device K times (K is an integer) every sampling period, said sampled data input and output device performing an input and output operation every sampling period, the input and output operation comprising generating M offset addresses for writing corresponding to said 1/M-fold decimation processing, generating M write addresses which differ from each other by modifying the basic address by the M offset addresses for writing, delivering the generated M write addresses to the storage device, generating one offset address for reading corresponding to said 1/M-fold decimation processing, generating one read address by modifying the basic address by the one offset address for reading, and delivering the generated one read address to the storage device.

5. A digital signal processing method comprising: a storing step of storing plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing in a storage device; a counting step of updating a count value of a counter every sampling period and generating the updated count value as a basic address; and an input or output step of performing an input and output operation every sampling period, the input and output operation comprising generating plural kinds of offset addresses corresponding, respectively, to the plural kinds of signal processing and not overlapping with each other, generating at least one write address or read address for the sampled data for each of the plural kinds of signal processing by modifying the basic address by at least one of the offset addresses corresponding to each of the plural kinds of signal processing, and delivering the generated at least one write address or read address to the storage device.