For controlling frequency and phase of an output clock signal dependent on a reference signal, a digital phase locked loop comprises a ring oscillator connected to a switch-over unit for generating the output clock signal. The ring oscillator has a plurality of serially arranged delay units. A phase comparator for comparing the phase of the reference signal and of the output clock signal. At least one switchable frequency divider unit is provided between the phase comparator and the output clock signal. A control unit controls the ring oscillator frequency by cut-in or cut-outs of delay units with the assistance of the switchover unit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A transmission equipment, comprising: a digital phase locked loop for controlling frequency and phase of an output clock signal dependent on a reference signal; the digital phase locked loop comprising a ring oscillator connected to a switch-over unit for generating the output clock signal, said ring oscillator comprising a plurality of serially arranged delay units; a phase comparator for comparing a phase of the reference signal and of the output clock signal; at least one switchable frequency divider unit connected between an output of the switch-over unit and the phase comparator; and a control unit for controlling a frequency of the ring oscillator by regularly switching between outputs of neighboring delay units of the ring oscillator with assistance of the switch-over unit to alter a number of the delay units which are effective within the ring oscillator.
2. The transmission equipment according to claim 1 wherein a further switchover unit is provided for generating a recovered output clock signal with a slightly different phase position and frequency compared to the output clock signal by a continuous, cyclical taking of the signals that are present at the outputs of the delay units of the ring oscillator and which respectively exhibit a different phase.
3. The transmission equipment digital phase locked loop according to claim 1 wherein the switchable frequency divider unit is inserted between the switch-over unit and the phase comparator so that output clock signals with different frequencies are generated given an unmodified reference signal.
4. The transmission equipment digital phase locked loop according to claim 1 wherein the switchover unit is a multiplexer.
5. The transmission equipment digital phase locked loop according to claim 1 wherein the delay units each comprise at least one of inverters and delay elements.
6. The transmission equipment digital phase locked loop according to claim 1 wherein the frequency divider unit comprises first and second divider counters whereby a counter reading of the first divider counter determines a number of clock periods wherein an output clock signal exhibiting a first frequency is present, and a counter reading of the second divider counter determines a number of corresponding clock periods wherein a second output clock signal exhibiting a second neighboring frequency is present; and an output clock signal having a frequency lying between a first and a second neighboring frequency is generated on the basis of the counter readings of the first and second divider counters.
7. The transmission equipment digital phase locked loop according to claim 6 wherein first and second circular counters are provided, whereby the first circular counter is started with a first whole-number start value N 1 and the second circular counter is started with a second whole-number start value N 2 , the respective first and second circular counters being started by a signal edge of the reference signal; a ratio of the first to the second start value N 1 /N 2 is determined by a required relationship of the reference signal to the output clock signal; and a first control signal for cut-in or cut-out of delay units within the ring oscillator is generated by the control unit on the basis of a sequence of a run-down of the first and second circular counters.
8. The transmission equipment digital phase locked loop according to claim 7 wherein third and fourth circular counters are provided, whereby the third circular counter is started with a third whole-number start value N 3 and the fourth circular counter is started by a fourth whole-number start value N 4 , the third and fourth circular counters being respectively started by a signal edge of the reference signal, and a counter reading of the third circular counter is respectively reduced by a count unit with a clock edge of a divided reference signal and a counter reading of the fourth circular counter is respectively reduced by a count unit with a clock edge of a divided output clock signal; a ratio of the third and fourth start value N 3 /N 4 is determined by a required relationship of the reference signal to the output clock signal; the counter reading of the third and fourth circular counters being compared at a zero axis crossing of one of the third and fourth counters; and based on a result of the comparison, a counter reading of one of the first and second divider counters is raised or lowered.
9. The transmission equipment digital phase locked loop according to claim 1 wherein a most recently generated form of said output clock signal continues to be generated given outage of the reference signal.
10. The transmission equipment according to claim 1 wherein a recovered output clock signal having a defined clock phase and frequency is respectively through-connected by a further switchover unit with assistance of a second control signal generated by the control unit; the second control signal is represented by a register value that is formed by a synchronous counter clocked by the reference signal; and the synchronous counter is respectively incremented or deincremented by a predetermined, whole-number increment value for raising or lowering a clock phase and frequency of the recovered output clock signal.
11. The digital phase locked loop according to claim 10 wherein a predetermined whole-number increment value is provided for offset formation between the reference signal and the recovered output clock signal.
12. The digital phase locked loop according to claim 1 wherein a plurality of further switchover units are provided for generating a plurality of recovered output clock signals exhibiting a differently slight frequency offset with respect to the reference signal.
13. A digital phase locked loop for controlling frequency and phase of an output clock signal dependent on a reference signal comprising: a ring oscillator connected to a switch-over unit for generating the output clock signal, said ring oscillator comprising a plurality of delay units; a phase comparator for comparing a phase of the reference signal and of the output clock signal; at least one switchable frequency divider unit; and a control unit for controlling a frequency of the ring oscillator by regularly switching between outputs of neighboring delay units of the ring oscillator with assistance of the switch-over unit to alter a number of the delay units which are effective within the ring oscillator.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 26, 2000
September 3, 2002
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.