A method for forming a lightly doped drain (LDD) field effect transistor uses very thin first sidewall spacers over the gate sidewalls, in which annealing/oxidation of the sidewall spacers results in (a) the rounding of corner portions of the gate structure sidewalls adjacent the gate oxide, and (b) a very low thermal consumption comprising a small portion of the total thermal budget. Secondary sidewall spacers of greater width are then formed to act as offsets in the introduction of N-type dopants into the substrate to form source and drain contact regions. The method may be varied to accommodate various design configurations and size scaling.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a transistor on a substrate, comprising: forming a dielectric layer on a substrate; forming a gate structure on the dielectric layer having a gate oxide layer formed on said dielectric layer and having a metal silicide layer formed on said gate oxide layer, said gate structure having a first sidewall and a second sidewall for defining therebetween within said substrate a first contact region, a channel region and a second contact region; and forming first and second subregions within the second contact region, each subregion having a dopant concentration that differs from that of the other subregion, said forming of each said first and second subregions comprising: depositing a thin conformal layer of dielectric material over said substrate; anisotropically etching said conformal layer of dielectric material for forming a first single thin layer sidewall spacer of dielectric material on said first sidewall and said second sidewall; performing an annealing/oxidation process on the dielectric material on said first sidewall and said second sidewall; forming a second single layer sidewall spacer overlying said first sidewall spacer; and introducing a first dopant into the substrate to form said first subregion, said first subregion being generally aligned with said second sidewall spacer.
2. The method of claim 1 , wherein the first sidewall spacer comprises an anisotropically etched layer of material having a thickness in the range of between about 50 and 150 Angstroms.
3. The method of claim 1 , wherein the second sidewall spacer comprises a layer of material having a thickness of in the range of about 2 to 20 times the thickness of said first sidewall spacer.
4. The method of claim 1 , wherein the second sidewall spacer comprises a layer of material having a thickness of about 550 Angstroms.
5. The method of claim 1 , wherein said first sidewall spacer is formed of one of silicon nitride and silicon dioxide.
6. A method of forming a transistor on a substrate, comprising: forming a dielectric layer on a substrate; forming a gate structure on a portion of the dielectric layer having at least a gate oxide layer formed on said dielectric layer and a metal silicide layer formed on said gate oxide layer, said gate structure having a first sidewall and a second sidewall for defining therebetween within the substrate a first contact region, a channel region and a second contact region; and forming first and second subregions within the second contact region, each subregion having a dopant concentration that differs from that of the other subregion, said forming each said first and second subregions comprising: depositing a first conformal layer of dielectric material over said substrate; etching said first layer of dielectric material for forming a first layer sidewall spacer of dielectric material on said first sidewall and said second sidewall; performing an annealing/oxidation process on the dielectric material on said first sidewall and said second sidewall; depositing a second conformal layer of dielectric material for forming a second layer sidewall spacer of dielectric material on at least portions of said first sidewall and said second sidewall; etching said second layer of dielectric material forming said second layer sidewall spacer of dielectric material on said first sidewall and said second sidewall; performing an annealing/oxidation process on the second layer of dielectric material on said first sidewall and said second sidewall; and introducing a first dopant into the substrate to form said first subregion, said first subregion being generally aligned with said second sidewall spacer.
7. The method of claim 6 , wherein said first sidewall spacer and said second sidewall spacer comprise one of silicon nitride and silicon dioxide.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 25, 2001
September 10, 2002
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