A controller issues a command to an HDD interface to transfer AV data stored in HDDs to a memory. The HDD interface, in compliance with the command, transfers the AV data stored in the HDDs to a memory mapped on a bus. A memory controller reads the AV data out of the bus, and writes the AV data into the memory. The controller outputs the address of the AV data to be outputted to the memory controller. The memory controller reads out the AV data of the designated address, and outputs them to an AV data output interface. And the AV data output interface outputs the AV data. The controller issues a command to the HDD interface memory to record the AV data stored in the memory into the HDDs. The HDD interface, in compliance with the command, reads the data out of a memory mapped on the bus, and stores them in the HDDs. The memory controller reads the AV data out of the memory, and outputs them to the bus. At the same time, the controller designates to the memory controller the address in the memory into which the AV data inputted from the AV data input interface are to be written. The memory controller reads the AV data out of the AV data input interface, and writes them into the designated memory. By accomplishing this series of actions in synchronism with the frame period, AV data are stored in the HDDs, and also AV data stored in the HDDs are outputted.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A video data output apparatus provided with a computer bus; storing means, connected to said bus, for storing video or audio data (hereinafter data); and output means, connected to said bus, for outputting the data, characterized in that: said output means has a memory for buffering said data; speed change means for changing the speed of said data; a second bus for connecting said memory, said speed change means and said bus; decoding means for decoding said data into video and audio signals; and control means for writing said data, written from said storing means into said output means via said bus, into said memory via said second bus, further reading said data out of said memory and transferring them to said speed change means via said second bus; and in accordance with an inputted frame reference signal, said control means outputs data of a frame from said memory to said speed change means in every fixed period of time t 1 , and said decoder reads the data of the frame at said speed change means in every fixed period of time t 1 in a predetermined format and decodes said data.
2. The video data output apparatus according to claim 1 , characterized in that said control means performs said data transfer from said memory to said speed change means when no writing from said storing means to said memory is taking place, and, if a request to write from said storing means to said memory arises during the transfer of said data, immediately suspends said data transfer and performs said data transfer from said storing means to said memory.
3. A video data input/output apparatus provided with a computer bus; storing means, connected to said bus, for storing data; and input/output means, connected to said bus, for inputting and outputting the data, characterized in that: said input/output means has a memory for buffering said data; speed change means for changing the speed of said data; second bus for connecting said memory, said speed change means and said bus; decoding means for decoding said data into video and audio signals; encoding means for converting video and audio signals into data; and control means for writing said data, written from said storing means into said input/output means via said bus, into said memory via said second bus, further transferring them from said memory to said speed change means via said second bus, or writing said data out of said speed change means into said memory via said second bus, and further outputting, when a read request is received from said storing means, said requested data from said memory to said storing means via said bus; and in accordance with an inputted frame reference signal, said control means inputs/outputs data of a frame from said memory to said speed change means in every fixed period of time t 1 , and said decoder reads data of a frame at said speed change means in every fixed period of time t 1 in a predetermined format and decodes said data.
4. The video data input/output apparatus according to claim 3 , characterized in that said control means performs said data transfer from said memory to said speed change means and said data transfer from said speed change means to said memory when no writing or reading from said storing means to said memory is taking place, and, if a request to write from said storing means to said memory or a request to read out of said memory arises during the transfer of said data, immediately suspends said data transfer and performs writing from said storing means to said memory or reading out of said memory to said storing means.
5. A video data input/output apparatus provided with a computer bus; storing means, connected to said bus, for storing data; and input/output means, connected to said bus, for inputting and outputting the data, characterized in that: said input/output means has first and second memories for buffering said data; first and second speed change means for changing the speed of said data; a second bus for connecting said first memory, said first speed change means and said bus; a third bus for connecting said second memory, said second speed change means and said bus; decoding means for decoding said data into video and audio signals; encoding means for converting video and audio signals into data; and control means for writing said data, written from said storing means into said input/output means via said bus, into said first and second memories via said second and third buses, further transferring them from said first and second memories to said second and third speed change means via said second and third buses, or writing said data out of said second speed change means into said first and second memories via said second and third buses, and further outputting, in compliance with a request from said storing means, the data from said first and second memories to said bus; and said control means performs said data transfer from said first memory to said first speed change means and said data transfer from said first speed change means to said first memory when no writing or reading from said storing means to said first memory is taking place, and, if a request to write from said storing means to said first memory and a request to read out of said first memory arise during the transfer of said data, immediately suspends said data transfer and performs writing from said storing means to said first memory or reading out of said first memory to said storing means; and performs said data transfer from said second memory to said second speed change means and said data transfer from said second speed change means to said second memory when no writing or reading from said storing apparatus to said second memory is taking place, and, if a request to write from said storing means to said second memory and a request to read out of said second memory arise during the transfer of said data, immediately suspends said data transfer and performs writing from said storing means to said second memory or reading out of said second memory to said storing means.
6. A video data input/output apparatus provided with a computer bus; storing means, connected to said bus, for storing data; and input/output means, connected to said bus, for inputting and outputting the data, characterized in that: said input/output means has a memory for buffering said data; speed change means for changing the speed of said data; a second bus for connecting said memory, said speed change means and said bus; a decoding means for decoding said data into video and audio signals; encoding means for converting video and audio signals into data; parity generating means for generating a parity from the output of said encoding means; data regenerating means for regenerating from part of said data and said parity the remaining data; and control means for writing said data, written from said storing means into said input/output means via said bus, and said parity into said memory via said second bus, further transferring them from said memory to said speed change means via said second bus, instructing said data generating means, when the writing of data from said storing means to said memory has delayed, to recalculate the data whose writing has delayed from the written data and parity, or writing said data out of said speed change means into said memory via said second bus, and further outputting, in compliance with a reading request from said storing means, said requested data from said memory to said storing means via said bus; and in accordance with an inputted frame reference. signal, said control means inputs/outputs data of a frame of said data from said memory to said speed change means in every fixed period of time t 1 , and said decoder reads data of a frame at said speed change means in every fixed period of time t 1 in a predetermined format and decodes said data.
7. The video data input/output apparatus according to claim 6 , characterized in that said control means performs said data transfer from said memory to said speed change means and said data transfer from said speed change means to said memory when no writing or reading from said storing means to said memory is taking place, and, if a request to write from said storing means to said memory or a request to read out of said memory arises during the transfer of said data, immediately suspends said data transfer and performs writing from said storing means to said memory or reading out of said memory to said storing means.
8. The video data input/output apparatus according to claim 7 , characterized in that said storing means comprises n HDDs, one frame of data is divided into 1/(n 1), each divided part of data is stored in one of said n 1 HDDs, and a generated parity is stored in the remaining 1 HDD.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 13, 1999
September 10, 2002
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