A multi-chip module is constructed by aligning prewired chips on a support wafer and depositing a nonconductive thermally conductive and electrically nonconductive material having a coefficient of thermal expansion that approximate that of the chips (e.g. silicon, silicon carbide, silicon germanium, germanium or SiCGe) to surround chips. After removal of the support wafer, processing of multi-chip module is finished with wiring on a shared surface of multi-chip module and chip surface.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic structure, comprising: a base structure on which a plurality of integrated circuit chips are mounted, the chips being elerically interconnected by conductive structures and each having a given coefficient of thermal expansion, the base structure being deposited on and surrounding said plurality of integrated circuit chips and being comprised of a material that is: thermally conductive; non-single crystalline; substantially electrically nonconductive; and has a coefficient of thermal expansion that approximates that of the chips.
2. An electronic structure as in claim 1 , wherein said material is selected from the group consisting of silicon, silicon carbide, silicon germanium, germanium, and SiCGe.
3. An electronic structure, comprising: a plurality of integrated circuit chips, each having first and second side faces and a plurality of end faces, and having a given coefficient of thermal expansion; and a nonconductive, non-single crystalline material deposited onto and overlaying one of said first and second side faces and substantially overlaying said plurality of end faces of said plurality of integrated circuit chips, said nonconductive material having a coefficient of the expansion similar to said given coefficient of thermal expansion of said plurality of integrated circuit chips.
4. A multi-chip module comprising: a plurality of wired integrated circuit chips, each of said integrated circuit chips surrounded on a bottom surface and any side surfaces by a non-single crystalline, semiconductive material deposited on said integrated circuit chips; a top surface of said material being continuous with a top surface of each of said plurality of said integrated circuit chips; and a wiring level on said at least one continuous surface.
5. A multi-chip module as in claim 4 , wherein said material has a coeffcient of thermal expansion approximately equal to a coefficient of thermal expansion of said plurality of wired integrated circuit chips.
6. A multi-chip module as in claim 4 , wherein said material is selected from the group consisting of silicon, silicon carbide, silicon germanium, germanium, and SiCGe.
7. A multi-chip module as in claim 4 , wherein said material is silicon.
8. An electronic structure, comprising: a base structure on which a plurality of integrated circuit chips are mounted, the chips being electrically interconnected by conductive structures, the base structure being deposited on and surrounding said plurality of integrated circuit chips other than an upper surface thereof, and being comprised of an amophous silicon material that is: thermally conductive; and does not impart substantial mechanical stress to said conductive structures.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 28, 2000
September 17, 2002
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