A circuit for controlling the storage of data in a memory element including a bistable device having a first input for receiving an address input and a second input for receiving a clock signal and circuitry for receiving the output of the bistable device and the clock signal and providing a write enable signal for the memory, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, the first and next transitions being in the same clock cycle.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A circuit for controlling the storage of data in a memory element, said circuit comprising: a) a bistable device having a first input for receiving an address input and a second input for receiving a clock signal; and b) circuitry for receiving an output of the bistable device and the clock signal and providing a write enable signal for said memory element, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making a next transition from the second state back to the first state, the first and next transitions being in a same clock cycle of the clock signal.
2. A circuit for controlling the storage of data in a memory element, said circuit comprising: a) a bistable device having a first input for receiving an address input and a second input for receiving a clock signal; and b) circuitry for receiving an output of the bistable device and the clock signal and providing a write enable signal for said memory element, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making a next transition from the second state back to the first state, the first and next transitions being in a same clock cycle of the clock signal; wherein the write enable signal is enabled for a duration that is substantially half a clock cycle of the clock signal.
3. A circuit as claimed in claim 2 , wherein the write enable signal is enabled for substantially a first half of the clock cycle.
4. A circuit for controlling the storage of data in a memory element, said circuit comprising: a) a bistable device having a first input for receiving an address input and a second input for receiving a clock signal; and b) circuitry for receiving an output of the bistable device and the clock signal and providing a write enable signal for said memory element, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making a next transition from the second state back to the first state, the first and next transitions being in a same clock cycle of the clock signal; wherein the bistable device is a latch.
5. A circuit as claimed in claim 4 , wherein said latch is a D-latch.
6. A circuit as claimed in claim 1 , wherein said circuitry comprises a AND gate.
7. A circuit as claimed in claim 1 , wherein a state of the write enable signal when enabled is dependent on an address of the first input when the clock signal is first enabled.
8. A write enable signal generator comprising a plurality of circuits, each said circuit being arranged to control storage of data in a memory element and comprising: a) a bistable device having a first input for receiving an address input and a second input for receiving a clock signal; and b) circuitry for receiving the output of the bistable device and the clock signal and providing a write enable signal for said memory element, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, said first and next transitions being in the same clock cycle, each of said circuits providing a write enable signal for a respective memory element of a memory array.
9. A memory arrangement comprising a write enable generator comprising a plurality of circuits, each said circuit being arranged to control storage of data in a memory element and comprising: a) a bistable device having a first input for receiving an address input and a second input for receiving a clock signal; and b) circuitry for receiving the output of the bistable device and the clock signal and providing a write enable signal for said memory element, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, said first and next transitions being in the same clock cycle, each of said circuits providing a write enable signal for a respective memory element of a memory array, said arrangement further comprising a plurality of memory elements, said memory elements being equal in number to said circuits.
10. A memory arrangement as claimed in claim 9 wherein said memory array is a FIFO memory array.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 2, 2000
September 17, 2002
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.