Techniques are described for providing mechanisms of data distribution to and collection of data from multiple memories in a data processing system. The system may suitably be a manifold array (ManArray) processing system employing an array of processing elements. Virtual to physical processing element (PE) identifier translation is employed in conjunction with a ManArray PE interconnection topology to support a variety of communication models, such as hypercube and such. Also, PE addressing nodes are based upon logically nested parameterized loops. Mechanisms for updating loop parameters, as well as exemplary instruction formats are also described.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus for performing virtual identification (VID) to physical identification (PID) translation for data elements to be accessed within local memory of a processing element (PE) whereby a direct memory access (DMA) controller can access PE local memories according to their VIDs, the apparatus comprising: an array of multiple PEs each having local PE memory; a DMA controller; and a memory maintained in the DMA controller for storing a processing element VID-to-PID table mapping processing element VIDs to processing element PIDs utilized by the DMA controller to access local memories according to their VIDs.
2. The apparatus of claim 1 wherein said memory is maintained in a core transfer unit of the DMA controller.
3. The apparatus of claim 2 wherein the core transfer unit (CTU) further comprises an address generation unit (AGU) which receives a CTU transfer instruction which specifies a starting address which is used by the AGU to generate an initial VID.
4. The apparatus of claim 3 wherein the initial VID controls the selection of one of the elements of the VID-to-PID lookup table through a multiplexer.
5. The apparatus of claim 4 further comprising a DMA bus for providing the selected PID as a first component of a PE address.
6. The apparatus of claim 5 wherein the AGU further operates to generate a PE memory offset which is sent as a second component of a PE address on the DMA bus.
7. The apparatus of claim 6 further comprising a local memory interface unit (LMIU) which is used to compare the PID sent on the DMA bus to a stored PID for any DMA access, if a match is detected then the LMIU accepts the access.
8. The apparatus of claim 3 wherein successive VIDs are generated in recursive fashion by the AGU.
9. The apparatus of claim 3 wherein successive VIDs are generated in recursive fashion by the AGU, and further comprising: a local memory interface unit for each processing element (PE) storing a VID for each PE.
10. The apparatus of claim 9 wherein a VID available to a particular LMIU or a DMA bus is compared with the stored VID in the LMIU and where a match occurs the LMIU accepts the access.
11. The apparatus of claim 1 wherein the VID-to-PID table is stored in a programmable register and the programmable register is loaded utilizing a DMA instruction.
12. The apparatus of claim 1 wherein the VID-to-PID table is stored in a programmable register and the programmable register loaded utilizing a direct write to the programmable register.
13. A processing apparatus comprising: a plurality of processing elements (PEs) communicatively connected by a bus, each PE comprising a register storing a virtual identification number (VID) identifying the PE; and a direct memory access (DMA) controller connected to the bus for accessing local data memory of the PEs, each data access at least partially identified by a VID; wherein during a common data to access multiple PEs, a PE responds to the data access if the VID stored in the register matches the VID of the data access.
14. The processing apparatus of claim 13 wherein each PE comprises a local memory interface unit (LMIU) which includes the register storing the VID.
15. The processing apparatus of claim 13 wherein the data access is a read access.
16. The processing apparatus of claim 13 wherein the data access is a write access.
17. The processing apparatus of claim 13 further comprising: means for updating the register.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 14, 2001
September 17, 2002
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