Sample hold circuit

1. A sample and hold circuit comprising: a common substrate; a sample and hold pulse generation circuit formed on said common substrate for generating a plurality of sample and hold pulses for sampling and holding a video signal, wherein a phase of said plurality of sample and hold pulses is shifted successively by a period of a master clock; a PLL circuit for generating said master clock in synchronism with a comparison reference signal provided externally and for generating a horizontal start pulse for use as a reference to determine a horizontal position of a displayed picture based on said video signal by dividing said master clock, wherein said PLL circuit is formed on said common substrate so that unwanted radiation is reduced regardless of a high frequency of said master clock; and a plurality of sample and hold units formed on said common substrate and having as inputs said video signal and said plurality of sample and hold pulses.

2. The sample and hold circuit as claimed in claim 1 , wherein said PLL circuit adjusts a phase of said master clock based on an externally provided signal.

3. The sample and hold circuit as claimed in claim 1 , further comprising means for controlling the timing of said horizontal start pulse based on said externally provided signal.

4. A liquid crystal display device comprising: a sample and hold circuit including: a common substrate, a sample and hold pulse generation circuit formed on said common substrate for generating a plurality of sample and hold pulses for sampling and holding a video signal, wherein a phase of said plurality of sample and hold pulses is shifted successively by a period of a master clock, a PLL circuit for generating said master clock in synchronism with a comparison reference signal provided externally and for generating a horizontal start pulse for use as a reference to determine a horizontal position of a displayed picture based on said video signal by dividing said master clock, wherein said PLL circuit is formed on said common substrate so that unwanted radiation is reduced regardless of a high frequency of said master clock; a plurality of sample and hold units formed on said common substrate and having as inputs said video signal and said plurality of sample and hold pulses; and a liquid crystal panel for displaying an output from said plurality of sample and hold units.

5. The liquid crystal display device as claimed in claim 4 , wherein said PLL circuit adjusts a phase of said master clock based on an externally provided signal.

6. The liquid crystal display device as claimed in claim 4 , further comprising means for controlling the timing of said horizontal start pulse based on said externally provided signal.