Method and apparatus for HASS testing of busses under programmable control

1. A testing method for testing a bus system of an electronic device, the bus system including a bus interface coupled with a bus characterized by a number of parameters, the testing method comprising: (a) injecting a set of stimulus patterns on the bus; (b) collecting information regarding operation of the electronic device corresponding to the stimulus patterns, including information identifying any error resulting from the set of stimulus patterns; (c) comparing the collected information with corresponding information collected during baseline testing; (d) determining, from step (c), whether the device is operating within a predetermined set of operating specifications; and (e) adjusting values of one or more of the parameters by varying one or more electronic characteristics of the bus interface in response to a set of digital control signals to obtain a set of operating and signaling parameters of the bus interface that cause the device to operate within the predetermined set of specifications.

2. The testing method in accordance with claim 1 , wherein the set of operating and signaling parameters include driver output voltage and receiver threshold voltage.

3. The testing method in accordance with claim 1 , wherein the set of operating and signaling parameters include bus signal propagation time.

4. The testing method in accordance with claim 1 , wherein the adjusting step includes adjusting bus signal propagation time to increase effective bus speed.

5. The testing method in accordance with claim 4 , wherein the adjusting step includes testing the bus at a series of different bus transfer speeds by selectively adjusting bus signal propagation times.

6. The testing method in accordance with claim 1 , wherein the adjusting step changes the values of the parameters within a range determined by the set of the operating specifications, and the method further includes determining degradation of the device by identifying an error resulting from the adjusted parameters.

7. The testing method in accordance with claim 1 , further comprising: (f) setting the parameter comprising a receiver threshold voltage to optimize noise response, the setting step comprising: (f1) raising the receiver threshold voltage until an error is identified at a corresponding first level of the receiver threshold voltage; (f2) lowering the receiver threshold voltage until an error is identified at a corresponding second level of the receiver threshold voltage; and (f3) setting the receiver threshold voltage at a third level between the first and second levels.

8. The testing method in accordance with claim 1 wherein step (e) comprises: (e1) increasing a parameter value; (e2) determining whether the system failed; (e3) if the system did not fail, saving the parameter value as the high point value and repeating steps (e1) and (e2) until the system fails; (e3) resetting the parameter to its initial value; (e4) decreasing the parameter value; and (e5) determining whether the system failed; (e6) if the system did not fail, saving the parameter value as the low point value and repeating steps (e4) and (e5) until the system fails; (e7) setting the parameter value to the midpoint of the high point and low point values.

9. The testing method in accordance with claim 1 wherein step (e) comprises: (e8) using a measured propagation delay to determine the fastest operating time for each possible setting of a device parameter; and (e9) using the correlation of the parameter value and speed to set the parameter to its best operating point.

10. A testing apparatus for testing a bus system of an electronic device, the bus system including a bus interface coupled with a bus characterized by a number of parameters, the testing apparatus comprising: a mechanism embedded in the device for injecting a set of stimulus patterns on the bus; a mechanism embedded in the device for collecting information regarding operation of the electronic device corresponding to the stimulus patterns, including information identifying any error resulting from the set of stimulus patterns; a mechanism for comparing the collected information with corresponding information collected during baseline testing; a mechanism for determining, in cooperation with the comparing mechanism, whether the device is operating within a predetermined set of operating specifications; and a mechanism embedded in the device for adjusting values of one or more of the parameters by varying one or more electronic characteristics of the bus interface in response to a set of digital control signals to obtain a set of operating and signaling parameters of the bus interface that cause the device to operate within the predetermined set of specifications.

11. The testing apparatus in accordance with claim 10 , wherein the set of operating and signaling parameters include driver output voltage and receiver threshold voltage.

12. The testing apparatus in accordance with claim 10 , wherein the set of operating and signaling parameters include bus signal propagation time.

13. The testing apparatus in accordance with claim 10 , wherein the adjusting mechanism is operable to adjust bus signal propagation time to increase effective bus speed.

14. The testing apparatus in accordance with claim 13 , wherein the adjusting mechanism is operable to test the bus at a series of different bus transfer speeds by selectively adjusting bus signal propagation times.

15. The testing apparatus in accordance with claim 10 , wherein the adjusting mechanism changes the values of the parameters within a range determined by the set of the operating specifications, and the testing apparatus further includes determining degradation of the device by identifying an error resulting from the adjusted parameters.

16. The testing apparatus in accordance with claim 10 , further comprising a mechanism for setting the parameter comprising a receiver threshold voltage to optimize noise response, the setting mechanism operable for raising the receiver threshold voltage until an error is identified at a corresponding first high level of the receiver threshold voltage; B) lowering the receiver threshold voltage until an error is identified at a corresponding second level of the receiver threshold voltage; and C) setting the receiver threshold voltage at a third level between the first and second levels.

17. The testing apparatus in accordance with claim 10 wherein the adjusting mechanism comprises: a first control mechanism which increases a parameter value; a first mechanism for determining whether the system failed; a mechanism cooperating with the first control mechanism and the first determining mechanism which saves the largest parameter value at which the system did not fail as the high point value; a mechanism for resetting the parameter to its initial value; a second control mechanism which decreases the parameter value; and a second mechanism for determining whether the system failed; a mechanism cooperating with the second control mechanism and the second determining mechanism which saves the smallest parameter value at which the system did not fail as the low point value; a mechanism for setting the parameter value to the midpoint of the high point and low point values.

18. The testing apparatus in accordance with claim 10 wherein the adjusting mechanism comprises: a mechanism which uses a measured propagation delay to determine the fastest operating time for each possible setting of a device parameter; and a mechanism which uses the correlation of the parameter value and speed to set the parameter to its best operating point.

19. A tuning apparatus for testing and adjusting a bus system of an electronic device, the bus system including a bus interface coupled with a bus characterized by a number of parameters, the tuning apparatus comprising: a mechanism embedded in the device for injecting a set of stimulus patterns on the bus; a mechanism embedded in the device for collecting information regarding operation of the electronic device corresponding to the stimulus patterns, including information identifying any error resulting from the set of stimulus patterns; a mechanism embedded in the device for adjusting values of one or more of the parameters by varying one or more electronic characteristics of the bus interface in response to a set of digital control signals to obtain a set of operating and signaling parameters of the bus interface that cause the device to operate within the predetermined set of specifications; and a mechanism for selecting a set of values of the parameters that provide a desired performance of the bus system, and for causing the adjusting mechanism to adjust the parameters to the selected set of values.

20. The tuning apparatus in accordance with claim 19 , wherein the set of operating and signaling parameters include driver output voltage and receiver threshold voltage.

21. The tuning apparatus in accordance with claim 19 , wherein the set of operating and signaling parameters include bus signal propagation time.

22. The tuning apparatus in accordance with claim 19 , wherein the adjusting mechanism is operable to adjust bus signal propagation time to increase effective bus speed.

23. The tuning apparatus in accordance with claim 22 , wherein the adjusting mechanism is operable to test the bus at a series of different bus transfer speeds by selectively adjusting bus signal propagation times.

24. The tuning apparatus in accordance with claim 19 , further comprising a mechanism for setting the parameter comprising a receiver threshold voltage to optimize noise response, the setting mechanism operable for A) raising the receiver threshold voltage until an error is identified at a corresponding first high level of the receiver threshold voltage; B) lowering the receiver threshold voltage until an error is identified at a corresponding second level of the receiver threshold voltage; and C) setting the receiver threshold voltage at a third level between the first and second levels.