A system for protecting data and correcting bit errors due to component failures includes a check bits generation unit which receives and encodes data to be protected. The check bits generation unit effectively partitions the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical groups, and additionally generates a global error correction. The global error correction code is equivalent to the result of generating individual error correction codes for each logical group and combining them in a predetermined manner. An error correction unit is coupled to receive the plurality of data bits and the check bits following storage or transmission. A global syndrome code is generated such that, with knowledge of the specific logical groups that have a single bit error, a value indicative of the location of the error in such groups may be derived from the global syndrome code.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A system for correcting data errors, comprising: a check bits generation unit for receiving a plurality of data bits, wherein said check bits generation unit is configured to generate a parity bit corresponding to each of a plurality of groupings of said data bits, and wherein said check bits generation unit is configured to generate a global error correction code equivalent to a predetermined combination of a set of error correction codes each individually associated with a corresponding one of said plurality of groupings, wherein the global error correction code is expressed using a smaller number of bits than a total number of bits of said set of error correction codes; an error correction unit coupled to receive said plurality of data bits, said parity bit for each of said plurality of groupings, and said global error correction code, wherein said error correction unit is configured to generate a parity error bit indicating whether a parity error exists for each of said plurality of groupings of said data bits as received, and wherein said error correction unit is configured to generate a syndrome code indicating a position of an error within any of said plurality of groupings, wherein said syndrome code depends upon a difference between said global error correction code and a regenerated global error correction code, and wherein said error correction unit is configured to correct the received data depending upon said parity error bits and said syndrome code.
2. The system as recited in claim 1 wherein said global error correction code is equivalent to a predetermined function of said set of error correction codes.
3. The system as recited in claim 2 wherein each bit of said global error correction code is equivalent to an exclusive OR of a predetermined set of bits of said set of error correction codes.
4. The system as recited in claim 1 wherein said global error correction code is a function of said set of error correction codes such that a combination of said global error correction code, said regenerated global error correction code, and said parity error bits uniquely determine said syndrome code.
5. The system as recited in claim 1 wherein said check bits generation unit is configured to generate an error correction code for each of said plurality of groupings of said data bits.
6. The system as recited in claim 1 wherein said global error correction code is equivalent to a result of bit-wise shifting at least some of said error correction codes and by XORing aligned bits of a plurality of resulting shifted error correction codes.
7. The system as recited in claim 6 wherein said plurality of data bits include a total of X groupings, and wherein said global error correction code is equivalent to a result of shifting said error correction code for a given ith group by i bit positions, wherein i 0 to X 1, and by XORing a plurality of resulting shifted error correction codes together.
8. The system as recited in claim 7 wherein said global error correction code is equivalent to a result of linearly shifting said error correction code for said given ith group by i bit positions.
9. The system as recited in claim 7 wherein said global error correction code is equivalent to a result of cyclically shifting said error correction code for said given ith group by i bit positions.
10. The system as recited in claim 6 wherein said error correction unit is configured to generate a global syndrome code by XORing said global error correction code with said regenerated global error correction code.
11. The system as recited in claim 10 wherein said plurality of data bits include a total of X groupings, and wherein said global error correction code is equivalent to a result of shifting said error correction code for a given ith group by i bit positions, wherein i 0 to X 1, and by XORing a plurality of resulting shifted error correction codes together.
12. The system as recited in claim 11 wherein each bit of said global syndrome code indicates whether the parity associated with an aligned column of bits of said plurality of resulting shifted error correction codes is the same as a parity associated with corresponding aligned bits of a plurality of shifted error correction codes based upon said regenerated error correction codes for said plurality of groupings.
13. The system as recited in claim 11 wherein said parity error bit for each of said plurality of groups and said global syndrome code are used to generate said syndrome code indicating a position of said error within any of said plurality of groupings.
14. The system as recited in claim 13 wherein said error correction unit is further configured to correct said error within any of said plurality of groupings.
15. The system as recited in claim 1 further comprising a component into which said plurality of data bits, said parity bit for each of said plurality of groupings, and said global error correction code are conveyed prior to being provided to said error correction unit.
16. The system as recited in claim 15 wherein said component includes a plurality of memory chips.
17. The system as recited in claim 16 wherein each bit within a particular grouping of data bits is stored in a separate memory chip, whereby no two bits of any given grouping are stored within the same memory chip.
18. The system as recited in claim 17 wherein bits at corresponding positions within the said plurality of groupings are stored within the same memory chip.
19. The system as recited in claim 15 wherein said component includes a plurality of communication paths.
20. The system as recited in claim 1 wherein said error correction code for each of said plurality of groupings is a single error correction Hamming code.
21. A method for correcting data errors comprising: receiving a plurality of data bits; generating a parity bit corresponding to each of a plurality of groupings of said data bits; generating a global error correction code equivalent to a predetermined combination of a set of error correction codes each individually associated with a corresponding one of said plurality of groupings, wherein the global error correction code is expressed using a smaller number of bits than a total number of bits of said set of error correction codes; receiving said plurality of data bits, said parity bit for each of said plurality of groupings, and said global error correction code; generating a parity error bit indicating whether a parity error exists for each of said plurality of groupings of said data bits as received; generating a syndrome code indicating a position of an error within any of said plurality of groupings, wherein said syndrome code depends upon a difference between said global error correction code and a regenerated global error correction codes and correcting the received data depending upon said parity error bits and said syndrome code.
22. The method as recited in claim 21 wherein said global error correction code is equivalent to a predetermined function of said set of error correction codes.
23. The method as recited in claim 22 wherein each bit of said global error correction code is equivalent to an exclusive OR of a predetermined set of bits of said set of error correction codes.
24. The method as recited in claim 21 wherein said global error correction code is a function of said set of error correction codes such that a combination of said global error correction code, said regenerated global error correction code, and said parity error bits uniquely determine said syndrome code.
25. The method as recited in claim 21 wherein said check bits generation unit is configured to generate an error correction code for each of said plurality of groupings of said data bits.
26. The method as recited in claim 21 wherein said global error correction code is equivalent to a result of bit-wise shifting at least some of said error correction codes and by XORing aligned bits of a plurality of resulting shifted error correction codes.
27. The method as recited in claim 26 wherein said plurality of data bits include a total of X groupings, and wherein said global error correction code is equivalent to a result of shifting said error correction code for a given ith group by i bit positions, wherein i 0 to X 1, and by XORing a plurality of resulting shifted error correction codes together.
28. The method as recited in claim 27 wherein said global error correction code is equivalent to a result of linerly shifting said error correction code for said given ith group by i bit positions.
29. The method as recited in claim 27 wherein said global error correction code is equivalent to a result of cyclically shifting said error correction code for said given ith group by i bit positions.
30. The method as recited in claim 26 further comprising generating a global syndrome code by XORing said global error correction code with said regenerated global error correction code.
31. The method as recited in claim 30 wherein said plurality of data bits include a total of X groupings, and wherein said global error correction code is derived by shifting said error correction code for a given ith group by i bit positions, wherein i 0 to X 1, and by XORing a plurality of resulting shifted error correction codes together.
32. The method as recited in claim 31 wherein each bit of said global syndrome code indicates whether the parity associated with an aligned column of bits of said plurality of resulting shifted error correction codes is the same as a parity associated with corresponding aligned bits of a plurality of shifted error correction codes based upon said regenerated error correction codes for said plurality of groupings.
33. The method as recited in claim 32 wherein said parity error bit for each of said plurality of groups and said global syndrome code are used to generate said syndrome code indicating a position of said error within any of said plurality of groupings.
34. The method as recited in claim 33 further comprising correcting said error within any of said plurality of groupings.
35. The method as recited in claim 21 further comprising conveying said plurality of data bits, said parity bit for each of said plurality of groupings, and said global error correction code into a component.
36. The method as recited in claim 35 wherein said component includes a plurality of memory chips.
37. The method as recited in claim 36 wherein each bit within a particular grouping of data bits is stored in a separate memory chip, whereby no two bits of any given grouping are stored within the same memory chip.
38. The method as recited in claim 37 wherein bits at corresponding positions within the said plurality of groupings are stored within the same memory chip.
39. The method as recited in claim 35 wherein said component includes a plurality of communication paths.
40. The method as recited in claim 21 wherein said error correction code for each of said plurality of groupings is a single error correction Hamming code.
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June 1, 1999
October 29, 2002
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