A process increases the etch control on the thin gate oxidation near the edges of a poly-silicon or amorphous silicon gate stack, minimizing the formation of micro-trenches while achieving nearly vertical profiles. In an example embodiment, a method for manufacturing a semiconductor gate stack a gate stack having an anti-reflective coating, has a pattern defined with a photoresist mask The unmasked areas of the gate stack are etched with a first etch. The first etch removes the anti-reflective layer and a majority of the poly or amorphous silicon from the unmasked areas. After the first etch, the photoresist mask is removed. Using the anti-reflective coating as a hard mask the poly or amorphous silicon is removed with a second etch from unmasked areas until the gate oxide exposed. An over etch removes any poly or amorphous silicon residues.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for etching a gate stack having a hard mask layer formed on a doped silicon layer on an insulating layer on a substrate, the hard mask layer having a pattern defined thereon, the pattern having masked areas and unmasked areas, the method comprising: etching through unmasked areas of the hard mask layer and a predetermined amount of the doped silicon layer with a first etch; removing the masked areas of the defined pattern; resuming etching of the doped silicon layer until the insulating layer is exposed with a second etch; and over-etching the remaining doped silicon layer with a third etch until silicon residues are cleared.
2. The method of claim 1 wherein the silicon layer is selected from the group including poly-silicon and amorphous silicon.
3. The method of claim 1 wherein in the insulating layer is selected from the group including silicon-rich oxide, silicon dioxide.
4. The method of claim 1 wherein the silicon layer is doped wit carriers selected from the group including N-type and P-type.
5. The method of claim 1 wherein the gate stack is etched to a profile in the range of about 85 to 90 .
6. The method of claim 1 wherein the first etch removes about 60% to 70% of the doped silicon layer.
7. The method of claim 1 wherein the first etch comprises: performing a breakthrough etch with a fluorine-containing gas selected from the group including CF 4 and NF 3 ; and performing a bulk etch with a gas mixture including Cl 2 , HBr, and CF 4 .
8. The method of claim 1 wherein removing the pattern defined in masked areas includes a wet-strip or ashing in an oxygen plasma.
9. The method of claim 1 wherein the second etch comprises, performing a breakthrough etch with a fluorine-containing gas selected from the group including CF 4 and NF 3 ; and performing an endpoint etch with a gas mixture including Cl 2 , HBr, and 80%HeO 2 .
10. The method of claim 1 wherein the third etch is a gas mixture including HBr, 80%HeO 2 , and He.
11. The method of claim 1 wherein the hard mask layer includes silicon oxy-nitride.
12. The method of claim 9 wherein the endpoint etch has a silicon-to-gate oxide selectivity ratio of at least 190:1.
13. The method of claim 8 wherein the breakthrough etch is introduced into the etch chamber at a flow rate in the range of about 80 sccm to 120 sccm.
14. The method of claim 7 wherein the bulk etch gases are introduced into the etch chamber at flow rates of about 5-30 sccm for Cl 2 , 50-150 sccm for HBr, and 5-50 sccm for CF 4 .
15. The method of claim 9 wherein the endpoint etch gases are introduced into the etch chamber at flow rates of about 5-30 sccm for Cl 2 , 50-200 sccm for HBr, and 5-30 sccm for 80%He O 2 .
16. The method of claim 10 wherein the third etch gases are introduced into the etch chamber at flow rates of about 100-300 sccm for HBr, 5-30 sccm for 80%He O 2 , and 100-500 sccm for He.
17. A method for etching a gate stack having an anti-reflective coating layer formed on a doped silicon layer on an insulating layer on a substrate, the anti-reflective coating layer having a pattern defined thereon, the pattern having masked areas and unmasked areas, the method comprising: etching through unmasked areas of the anti-reflective coating layer and the majority of the doped silicon layer with a first etch; removing the masked areas of the defined pattern on the anti-reflective coating layer, using the anti-reflective coating layer as a hard mask and resuming etching of the doped silicon layer until the insulating layer is exposed with a second etch; and over-etching the remaining doped silicon layer with a third etch until silicon residues are cleared.
18. The method of claim 17 , wherein the first etch comprises, performing a first breakthrough etch with a fluorine-containing gas selected from the group including CF 4 and NF 3 ; and performing a bulk etch with a gas mixture including Cl 2 , HBr, and CF 4 ; wherein the second etch comprises, performing a second breakthrough etch with a fluorine-containing gas selected from the group including CF 4 and NF 3 ; and performing an endpoint etch with a gas mixture including Cl 2 , HBr, and 80%HeO 2 ; wherein the third etch comprises, performing an over-etch with a gas mixture including HBr, 80%HeO 2 , and He.
19. The method of claim 18 , wherein the breakthrough etch is introduced into the etch chamber at a flow rate in the range of about 80 sccm to 120 sccm; wherein the bulk etch gases are introduced into the etch chamber at flow rates of about 5-30 sccm for Cl 2 , 50-150 sccm for HBr, and 5-50 sccm for CF 4 ; wherein the endpoint etch gases are introduced into the etch chamber at flow rates of about 5-30 sccm for Cl 2 , 50-200 sccm for HBr, and 5-30 sccm for 80%He O 2 ; and wherein third etch gases are introduced into the etch chamber at flow rates of about 100-300 sccm for HBr, 5-30 sccm for 80%He O 2 , and 100-500 sccm for He.
20. The method of claim 19 wherein the gate stack is etched to a profile in the range of about 85 to 90 .
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 25, 2000
November 5, 2002
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