A nonvolatile memory device includes: a first insulating film, a selection gate, a second insulating film and an erase gate layered on a semiconductor substrate; sidewalls formed in contact with both sides of the selection gate, the erase gate and the second insulating film; a third insulating film formed over an upper surface and an edge of the erase gate; a fourth insulating film formed on the surface of the semiconductor substrate in contact with the sidewalls; a floating gate overlapping the erase gate at a certain width; a dielectric film formed on the floating gate; a source/drain formed in the semiconductor below the floating gate and one of the sidewalls; and a control gate formed on the entire surface including the erase and floating gate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nonvolatile memory device comprising: a selection gate and an erase gate insulated from each other and aligned with each other on a semiconductor substrate and layered in a first direction; a floating gate overlapping one side of the selection and the erase gates; and a control gate formed on an entire surface including the floating gate and the erase gate in a second direction, the second direction being perpendicular to the first direction.
2. The nonvolatile memory device as claimed in claim 1 , further comprising sidewalls formed at both sides of the selection gate and the erase gate, wherein at least one of the sidewalls is adjacent to both the selection gate and the erase gate.
3. The nonvolatile memory device as claimed in claim 1 , further comprising source/drain formed in the semiconductor substrate below the floating gate and the erase gate.
4. The nonvolatile memory device as claimed in claim 1 , wherein the selection gate and the erase gate are self-aligned.
5. The nonvolatile memory device as claimed in claim 1 , further comprising insulating films formed to cover an upper surface and edges of the erase gate.
6. The nonvolatile memory device as claimed in claim 1 , further comprising sidewalls formed at both sides of the selection gate and the erase gate, wherein at least one of the sidewalls has a planar surface, and wherein the planar surface is adjacent to both the selection gate and the erase gate.
7. The nonvolatile memory device as claimed in claim 1 , further comprising sidewalls formed at both sides of the selection gate and the erase gate, and further comprising an insulating layer formed between the substrate and the selection gate, floating gate and control gate, but not between the substrate and the sidewalls.
8. The nonvolatile memory device as claimed in claim 1 , further comprising a first insulating layer between and adjacent to both the floating gate and the control gate, and further comprising a second insulating layer between and adjacent to both the erase gate and the control gate.
9. The nonvolatile memory device as claimed in claim 1 , wherein the floating gate is over only one side of the erase gate.
10. A nonvolatile memory device comprising: a first insulating film, a selection gate, a second insulating film and an erase gate layered on a semiconductor substrate; sidewalls formed in contact with both sides of the selection and erase gates including the first and second insulating films; a third insulating film formed over an upper plane and upper edges of the erase gate; a fourth insulating film formed on a surface of the semiconductor substrate at both sides of the sidewalls; a floating gate overlapping one side of the erase gate at a certain width; a dielectric film formed on the floating gate; a source/drain aligned with the floating gate and at least one of the sidewalls, and formed on the surface of the semiconductor substrate; and a control gate formed on an entire surface including the erase gate and the floating gate.
11. A method of manufacturing a nonvolatile memory device, comprising: layering a first insulating film, a first conductive layer, a second insulating film and a second conductive layer on a semiconductor substrate; forming an erase gate having the second conductive layer and a selection gate having the first conductive layer in a first direction, by patterning the second conductive layer, the second insulating film, the first conductive layer and the first insulating film; forming sidewalls in contact with both sides of the layered selection gate and erase gate by forming a third insulating film on an entire surface including the selection and erase gate and etching back the third insulating film; forming a fourth insulating film over an upper plane and upper edges of the erase gate; forming a floating gate overlapping one side of the erase gate at a certain width by forming a third conductive layer on the fourth insulating film and patterning the third conductive layer; forming a fifth insulating film on the floating gate; forming source/drains in the surface of the semiconductor substrate using the floating gate and the erase gate including the sidewalls as masks; and forming a control gate in a second direction vertical to the floating and erase gates by forming a fourth conductive layer on the entire surface including the floating and erase gates and patterning the fourth conductive layer.
12. The method as claimed in claim 11 , further comprising forming an insulating film on the surface of the semiconductor substrate before forming the floating gate.
13. The method as claimed in claim 11 , wherein the fifth insulating film is formed by layering an oxide/nitride/oxide (ONO) film using the CVD process.
14. The method as claimed in claim 13 , wherein the ONO film has a thickness of oxide of 55 , nitride of 170 , and oxide of 80 .
15. The method as claimed in claim 11 , wherein the patterning of the second conductive layer, the second insulating film, the first conductive layer and the first insulating layer is performed by photolithography and etching processes so that the selection gate and the erase gate are self-aligned.
16. The method as claimed in claim 11 , wherein the second insulating film is formed with a thickness of 1500 2000 by the CVD process.
17. The method as claimed in claim 11 , wherein the fourth insulating film is formed with a thickness under 250 to move the electrons in the floating gate to the erase gate.
18. The method as claimed in claim 11 , wherein the first, second, third and fourth conductive layers are formed of a polysilicon layer with a thickness under 2000 .
19. The method as claimed in claim 11 , wherein the sidewalls are so formed that the upper edges of the erase gate are exposed.
20. The method as claimed in claim 11 , further comprising an insulating film for the floating gate on the surface of the semiconductor substrate at both sides of the sidewalls, forming the fourth insulating film.
21. The method as claimed in claim 20 , wherein the insulating film for the floating gate is formed with a thickness under 150 .
22. A The method as claimed in claim 11 , wherein the sidewalls are formed at both sides of the erase gate and selection gate including the first and second insulating films.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 22, 2000
November 5, 2002
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.