A data processing system including a processor having a load/store unit and a method for correcting effective address aliasing. In the load/store unit within the processor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. A real address tag is utilized to correct for effective address aliasing within the load/store unit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A processor comprising a load/store unit having a level one (L1) cache and coupled to a memory subsystem, the load/store unit further having a real address tag array for correcting effective address aliasing within the load/store unit, wherein the load/store unit further comprises: circuitry for receiving an L1 cache reload from the memory subsystem, circuitry for comparing a real address of the L1 cache reload to addresses in the real address tag array, circuitry for calculating an effective address corresponding to the real address of the L1 cache reload if the comparison results in a hit, circuitry for using the calculated effective address to clear an effective address tag array of any corresponding effective address in the effective address tag array; and circuitry for reloading the L1 cache using the calculated effective address.
2. The processor as recited in claim 1 , wherein the load/store unit further comprises: circuitry for receiving an address corresponding to a store request, circuitry for comparing the address of the store request to addresses in the real address tag array; circuitry for calculating an effective address corresponding to the address of the store request if the comparison results in a hit, and circuitry for loading the L1 cache using the calculated effective address.
3. The processor as recited in claim 2 , wherein the load/store unit further comprises circuitry for storing to the memory subsystem using the calculated effective address.
4. A processor comprising a load/store unit having a level one (L1) cache and coupled to a memory subsystem, the load/store unit further having a real address tag array for correcting effective address aliasing within the load/store unit, wherein the load/store unit further comprises: circuitry for receiving a snoop invalidate from the memory subsystem; circuitry for comparing a real address of the snoop invalidate to addresses in the real address tag array; circuitry for calculating an effective address corresponding to the real address of the snoop invalidates if the comparison results in a hit, and circuitry for using the calculated effective address to clear an effective address tag array of any corresponding effective address in the effective address tag array.
5. In a processor having a load/store unit coupled to an L1 cache and a level two (L2) cache, a method comprising the steps of receiving a real address within a real address tag array in the load/store unit, and correcting effective address aliasing within the load/store unit corresponding to the real address, wherein the correcting step further comprises the steps of receiving an L1 cache reload from the L2 cache, comparing a real address of the L1 cache reload to addresses in the real address tag array, calculating an effective address corresponding to the real address of the L1 cache reload if the comparison results in a hit, using the calculated effective address to clear an effective address tag array of any corresponding effective address in the effective address tag array, and reloading the L1 cache using the calculated effective address.
6. The method as recited in claim 5 , wherein the correcting step further comprises the steps of receiving a snoop invalidate from the L2 cache, comparing a real address of the snoop invalidate to addresses in the real address tag array, calculating an effective address corresponding to the real address of the snoop invalidate if the comparison results in a hit, and using the calculated effective address to clear an effective address tag array of any corresponding effective address in the effective address tag array.
7. The method as recited in claim 5 , wherein the correcting step further comprises the steps of: receiving an address corresponding to a store request; comparing the address of the store request to addresses in the real address tag array; calculating an effective address corresponding to the address of the store request if the comparison results in a hit; and loading the L1 cache using the calculated effective address.
8. The method as recited in claim 7 , wherein the correcting step further comprises the step of storing to the L2 cache using the calculated effective address.
9. A data processing system comprising: a processor including a load/store unit; a primary cache, a secondary cache, and circuitry for coupling the processor to the primary cache and the secondary cache, wherein the load/store unit further comprises: a real address tag array for correcting effective address aliasing within the load/store unit, wherein the load/store unit further comprises: a latch receiving a primary cache reload from the secondary cache; a tag comparator comparing a real address of the primary cache reload to addresses in the real address tag array; circuitry for calculating an effective address corresponding to the real address of the primary cache reload if the comparison results in a hit; a clear tag port using the calculated effective address to clear an effective address tag array of any corresponding effective address in the effective address tag array; and circuitry for reloading the primary cache using the calculated effective address.
10. The system as recited in claim 9 , wherein the real address tag array is operable for correcting effective address aliasing for store, snoop invalidate and cache reload operations.
11. The system as recited in claim 9 , wherein the load/store unit further comprises a latch receiving an address corresponding to a store request from a store reorder queue in the load/store unit; a tag comparator comparing the address of the store request to addresses in the real address tag array; circuitry for calculating an effective address corresponding to the address of the store request if the comparison results in a hit, and circuitry for loading the primary cache using the calculated effective address.
12. The system as recited in claim 11 , wherein the load/store unit further comprises circuitry for storing to the secondary cache using the calculated effective address.
13. A data processing system comprising a processor including a load/store unit, a primary cache, a secondary cache, and circuitry for coupling the processor to the primary cache and the secondary cache, wherein the load/store unit further comprises a real address tag array for correcting effective address aliasing within the load/store unit wherein the load/store unit further comprises a latch receiving a snoop invalidate from the secondary cache, a tag comparator comparing a real address of the snoop invalidate to addresses in the real address tag array, circuitry for calculating an effective address corresponding to the real address of the snoop invalidate if the comparison results in a hit; and a clear tag port, coupling the real address tag array to an effective address tag array using the calculated effective address to clear the effective address tag array of any corresponding effective address in the effective address tag array.
14. In a processor having a load/store unit coupled to an L1 cache and an L2 cache, a method comprising the steps of: receiving a real address within a real address tag array in the load/store unit, and correcting effective address aliasing within the load/store unit corresponding to the real address, wherein the correcting step further comprises the steps of: receiving a snoop invalidate from the L2 cache; comparing a real address of the snoop invalidate to addresses in the real address tag array; calculating an effective address corresponding to the real address of the snoop invalidate if the comparison results in a hit; and using the calculated effective address to clear an effective address tag array of any corresponding effective address in the effective address tag array.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 8, 1999
November 5, 2002
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