When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping is generally supplied to an A/D converter as generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal oputput by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A solid state imaging system comprising: a solid state image sensing element having a sensor unit for generating signal charges and a transferring unit for transferring said signal charges read out from said image sensing unit in response to transfer clocks, said image sensing element outputting an electrical signal corresponding to said signal charges, said electrical signal including at least an empty transmission signal, a first optical black signal and an image signal sequentially along a time axis in a unit cycle; and a clamp circuit for clamping said electrical signal to a reference voltage over a period of time that includes an inhibit period of said transfer clocks.
2. A solid state imaging system according to claim 1 wherein said inhibit period of said transfer clocks exists within a period of said empty transmission signal.
3. A solid state imaging system according to claim 1 wherein said electrical signal further comprises a second optical black signal just after said image signal in said cycle.
4. A solid state imaging system according to claim 1 further comprising an A-to-D converter connected to said clamp circuit for converting the clamped electrical signal to a digital signal.
5. A solid state imaging system according to claim 1 further comprising a sample and hold circuit connected between said image sensing element and said clamp circuit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 8, 1996
November 12, 2002
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