Described is a clock circuit for supplying synchronized signals to a plurality of circuits. The clock circuit includes a clock generator and a driver for outputting the clock signals inputted from the clock generator with a delay time so that a difference among arrival times of the clock signals is minimized among the plurality of circuits.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A clock circuit which supplies clock signals synchronized with each other to a plurality of circuits, comprising: a clock generator; and a driver for outputting each clock signal supplied from clock generator, each signal being outputted with a delay from other signals to corresponding one of said plurality of circuits so that a difference among arrival times of said clock signals is minimized among said plurality of circuits, wherein said driver has a plurality of delay times previously determined depending on a load state of each of said circuits, and selects the delay time for each of said circuits supplied with the clock signals, thereby outputting the clock signal after delaying it by the delay time.
2. The circuit according to claim 1 , wherein said clock circuit further includes a driver selection circuit for selecting the drive circuit corresponding to one of the plurality of circuits and a delayed clock signal from the drive circuit selected by the driver selection circuit is supplied to the corresponding circuit.
3. The circuit according to claim 2 , further including an initial setting circuit which determines the circuit supplied with the clock signal, and outputs a selection signal for selecting the drive circuit which has the delay time corresponding to the load state of the circuit detected to the driver selection circuit.
4. The circuit according to claim 3 , wherein said initial setting circuit decides the load state of the circuit and outputs the selection signal for selecting the drive circuit which has the delay time corresponding to the decided load state of the circuit to the driver selection circuit, thereby switching the output of the drive circuit to a delayed clock output of the selected drive circuit when a low frequency clock signal is supplied to the circuits at the time of starting the plurality of circuits.
5. A computer system comprising: a CPU; a memory controller; a memory; and a clock circuit for supplying clock signals in synchronization with each other, the clock circuit further comprising: a clock generator; and a driver for receiving clock signals supplied from the clock generator and outputting one or more clock signals with a delay time predetermined in accordance with each circuit of the CPU, the memory controller and the memory to be supplied with the clock signal such that a difference of arrival times of the clock signals among the CPU, the memory controller and the memory is minimized.
6. The computer system according to claim 5 , wherein the memory includes an already incorporated memory and an additionally incorporated memory added according to demand.
7. The computer system according to claim 5 , further including: a drive selection circuit for selecting a corresponding drive circuits, a delayed clock output is supplied from the drive circuit selected by the drive selection circuit, and wherein the driver is composed of a plurality of drive circuits, each of the driver circuits has a delay time predetermined in accordance with the load state of the circuit supplied with the clock signal.
8. The computer system according to claim 7 , further including an initial setting circuit for deciding the circuit to be supplied with the clock signal, and a selection signal for selecting the drive circuit having the delay time in accordance with the detected circuit is outputted to the drive selection circuit.
9. The computer system according to claim 8 , wherein the initial setting circuit decides the load state of the circuit and outputs the selection signal for selecting the drive circuit having the delay time in accordance with the decided load state of the circuit when a low frequency clock signal is supplied to the circuit at the time of starting the plurality of circuits, thereby changing the output of the drive circuit to a delay clock output of the drive circuit.
10. A method for supplying clock signals in synchronization with each other to a plurality of circuits, comprising the steps of: setting a delay time of the clock signals for each circuit of the plurality of circuits, wherein the delay time of the clock signal is set in accordance with a load state of the circuit to be supplied with the clock signal; and outputting the clock signals with the delay time determined for each circuit so that a difference of arrival times of said clock signal is minimized among the plurality of circuits.
11. The method according to claim 10 , wherein the step for outputting said clock signal with the delay time includes: supplying a low frequency clock signal to the circuit at the time of starting the plurality of circuits; deciding the load state of the circuit and selecting the delay time predetermined in accordance with the decided load state of the circuit; and supplying a normal clock signal which is delayed by the selected delay time instead of the low frequency clock signal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 7, 1999
November 26, 2002
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