A method of manufacturing a semiconductor chip that has electrode pads on the chip front surface and disposed inside a conductive outer ring. A film circuit is disposed on the chip front surface side. External connection thermals are formed on the film circuit so as to project there from. First leads electrically connect part of the electrode pads to part of the external connection terminals. A second lead electrically connects a grounding or power supply electrode pad to the outer ring, and a third lead electrically connects a grounding or power supply external connection terminal to the outer ring.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A manufacturing method of a lead frame, comprising the steps of: forming a plurality of leads on a surface of a metal base of a laminated structure by metal plating with at least one of the plurality of leads formed as to extend to an outer ring portion of the metal base; separating the plurality of leads from each other by selectively removing the metal base by etching; and forming bumps on tips of the respective separated leads, and then bonding a reinforcement plate to lead surfaces excluding bump forming regions thereof; filling the outer ring portion with a conductor paste that is in contact with the at least one of the plurality of leads and the reinforcement plate.
2. A manufacturing method of a lead frame, comprising the steps of: forming a plurality of leads on a surface of a metal base of a laminated structure by metal plating with at least one of the plurality of leads formed as to extend to an outer ring portion of the metal base; covering given regions of the leads with an insulating film; and layering a solder material on the leads at given positions by electrolytic plating with the insulating film used as a mask, and, immediately thereafter, shaping the solder material into ball shapes by reflowing; filling the outer ring portion with a conductor paste that is in contact with the at least one of the plurality of leads and the reinforcement plate.
3. A manufacturing method of a semiconductor device, comprising the steps of: forming a plurality of leads on a surface of a metal base of a laminated structure by metal plating with at least one of the plurality of leads formed as to extend to an outer ring portion of the metal base; covering given regions of the leads with an insulating film; separating the plurality of leads from each other by selectively removing the metal base by etching; forming bumps on tips of the respective separated leads, and then bonding a reinforcement plate to lead surfaces excluding bump forming regions thereof; and connecting electrodes of a semiconductor chip to the bumps; filling the outer ring portion with a conductor paste that is in contact with the at least one of the plurality of leads and the reinforcement plate.
4. The manufacturing method according to claim 3 , further comprising the step of laying a solder material on the leads at given positions by electrolytic plating with the insulating film used as a mask, and, immediately thereafter, shaping the solder material into ball shapes by reflowing.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 31, 2001
December 10, 2002
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