A semiconductor device that optimally controls a current supply of internal power supply voltage generation circuits in accordance with the number of banks that are simultaneously activated. A control circuit adjusts the activated number of internal power supply voltage generation circuits in response to activation signals of the banks.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a plurality of banks; a plurality of internal power supply voltage generation circuits for generating an internal power supply voltage that is provided to the banks; and at least one control circuit connected to the internal power supply voltage generation circuits for controlling the internal power supply voltage generation circuits, wherein the control circuit adjusts a current supply amount of the internal power supply voltage generation circuits in accordance with a current consumption of at least one of activated ones of the banks by changing the number of internal power supply voltage generation circuits that are to be activated.
2. The semiconductor device according to claim 1 , wherein the control circuit adjusts the number of the internal power supply voltage generation circuits that are activated in accordance with the operational frequency.
3. The semiconductor device according to claim 2 , wherein the operational frequency of the semiconductor device corresponds to a cycle time that starts when each of the banks are activated and ends when each of the banks are activated the next time.
4. The semiconductor device according to claim 1 , wherein each of the banks are activated in response to an external signal, and wherein the control circuit selects one or more of the internal power supply voltage generation circuits that are to be activated in accordance with the position of the one or more banks that are activated.
5. The semiconductor device according to claim 1 , wherein the plurality of banks includes a first bank and a second bank located in the vicinity of the first bank, wherein the plurality of internal power supply voltage generation circuits includes a plurality of first internal power supply voltage generation circuits assigned to the first bank and a plurality of second internal power supply voltage generation circuits assigned to the second bank, and wherein, when the first bank is activated, the control circuit activates at least one of the first and second internal power supply voltage generation circuits.
6. The semiconductor device according to claim 5 , wherein, when the first bank is activated, the control circuit activates all of the first internal power supply voltage generation circuits and at least one of the second internal power supply voltage generation circuits.
7. A method for generating an internal power supply voltage of a semiconductor device having a plurality of banks and a plurality of internal power supply voltage generation circuits, wherein the plurality of banks include a first bank and a second bank located in the vicinity of the first bank, and the plurality of internal power supply voltage generation circuits include at least one internal power supply voltage generation circuit associated with the first bank and at least one second internal power supply voltage generation circuit associated with the second bank, the method comprising the steps of: determining the total number of internal power supply voltage generation circuits that are to be activated in accordance with a current consumption of at least one of activated ones of the banks; and providing the at least one activated ones of the banks with an internal power supply voltage by activating the determined number of internal power supply voltage generation circuits, wherein, when the first bank is activated, at least one of the first internal power supply voltage generation circuits and at least one of the second internal power supply voltage generation circuits are activated.
8. A method for generating an internal power supply voltage of a semiconductor device having a plurality of banks that include a first bank and a second bank located in the vicinity of the first bank, the method comprising the steps of: assigning a plurality of internal power supply voltage generation circuits to each of the banks, wherein the internal power supply voltage generation circuits generate internal power supply voltage provided to the banks, and wherein a current supply capacity of each of the internal power supply voltage generation circuits is equal to or less than a current consumption of when one of the banks is activated; and activating at least one of the internal power supply voltage generation circuits assigned to the first and second banks when the first bank is activated.
9. A method for generating an internal power supply voltage having a plurality of banks and a plurality of internal power supply voltage generation circuits for generating an internal power supply that is provided to the banks, the method comprising the steps of: detecting a number M of the activated ones of the banks; determining a number X of the internal power supply voltage generation circuits that are to activated in accordance with the number M, the number X of the internal power supply voltage circuits that are to be activated being expressed by X<N M, wherein N represents the number of internal power supply voltage generation circuits that are activated when only one of the banks is activated.
10. A semiconductor device comprising: a plurality of banks; a plurality of internal power supply voltage generation circuits connected to the banks for generating an internal power supply voltage when activated that is provided to the banks; and a control circuit connected to the internal power supply voltage generation circuits for controlling the internal power supply voltage generation circuits, wherein the control circuit selectively activates the internal power supply voltage generation circuits and changes the number of internal power supply voltage generation circuits that are to be activated in accordance with the number of activated ones of the banks.
11. The semiconductor device according to claim 10 , wherein the plurality of banks includes a first bank and a second bank located in the vicinity of the first bank, wherein the plurality of internal power supply voltage generation circuits includes a plurality of first internal power supply voltage generation circuits assigned to the first bank and a plurality of second internal power supply voltage generation circuits assigned to the second bank, and wherein, when one of the banks are activated, the control circuit activates at least one of the first and second internal power supply voltage generation circuits.
12. The semiconductor device according to claim 10 , wherein, when the first bank is activated, the control circuit activates all of the first internal power supply voltage generation circuits and at least one of the second internal power supply voltage generation circuits.
13. The semiconductor device according to claim 10 , wherein each of the banks is connected to an internal power supply voltage generation circuit group formed by a plurality of the internal power supply voltage generation circuits.
14. The semiconductor device according to claim 13 , wherein the control circuit activates substantially the same number of the internal power supply voltage generation circuits in each of the internal power supply voltage generation circuit groups in accordance with a current consumption of the activated ones of the banks.
15. A semiconductor device comprising: a plurality of banks; a plurality of internal power supply voltage generation circuits for generating an internal power supply voltage that is provided to the banks; and at least one control circuit connected to the internal power supply voltage generation circuits for controlling the internal power supply generation circuits, wherein the control circuit adjusts a current supply amount of the internal power supply voltage generation circuits, which has a constant margin relative to a current consumption of at least one of activated ones of the banks.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 15, 2001
December 17, 2002
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