Multi-chip packaging structure

1. A multi-chip packaging structure, comprising: a substrate having a top surface and a bottom surface, the substrate having an opening defined substantially in a middle section of the substrate through the top surface and the bottom surface, wherein the substrate includes at least one via contact; a first chip having a first active surface and a first non-active back surface, wherein the first chip has a plurality of first bonding pads on the first active surface, the first chip is attached to the bottom surface of the substrate such that the first chip is electrically connected to the top surface of the substrate through the opening; at least one second chip having a second active surface and a second non-active back surface, wherein the second chip has a plurality of second bonding pads on the second active surface, the second chip is attached to the top surface of the substrate by its second non-active back surface and electrically connected to the top surface of the substrate, and wherein the second chip is externally electrically connected to an external unit through the via contact; and a heat sink directly attached on the first back non-active surface of the first chip and thermally coupled with the first chip, wherein the heat sink is not in direct contact with the bottom surface of the substrate.

2. The multi-chip packaging structure of claim 1 , wherein the second back surface of the second chip faces the first surface of the substrate and is secured thereon by the second bonding pads electrically connected to the conductive areas by at least one bonding wire.

3. The multi-chip packaging structure of claim 1 , wherein the second active surface of the second chip faces the first surface of the substrate as arranged with the second bonding pads electrically connected to the conductive areas by at least one solder bump.

4. The multi-chip packaging structure of claim 1 , wherein the second surface of the substrate including a recess sized and shaped to receive the first chip with the first chip located inside the recess.

5. A multi-chip ball grid array package, comprising: a laminated substrate having a top surface and a bottom surface, the laminated substrate having an opening defined substantially in a middle section of the laminated substrate through the top surface and the bottom surface, and the laminated substrate having at least one via contact and a plurality of solder ball pads located on the bottom surface thereof; a first chip having a first active surface and a first non-active back surface, wherein the first chip is attached to the bottom surface of the substrate; a plurality of first bonding pads formed on a central region of the first active surface of the first chip and are exposed by the opening such that the first chip is electrically connected to the top surface of the laminated substrate through the opening; at least one second chip having a second active surface and a second non-active back surface, wherein the second chip is attached to the top surface of the laminated substrate by its second non-active back surface; a plurality of second bonding pads formed on a peripheral region of the second active surface of the second chip, wherein the second bonding pads are electrically connected to the top surface of the substrate and wherein the second chip is externally electrically connected to an external unit through the via contact; a heat sink directly attached on the first non-active back surface of the first chip and thermally coupled with the first chip, wherein the heat sink is not in direct contact with the bottom surface of the substrate; an encapsulant at least enveloping connections between the first bonding pads, the second bonding pads and the via contact; and a plurality of solder balls placed on the solder ball pads, wherein the second chip is externally electrically connected to the solder balls through the via contact.

6. The multi-chip ball grid array package of claim 5 , wherein the second surface of the laminated substrate includes a recess sized and shaped to receive the first chip with the first chip located inside the recess.

7. The multi-chip ball grid array package of claim 5 , wherein the second back surface of the second chip faces the first surface of the laminated substrate and is secured on it with the second bonding pads electrically connected to the conductive connections by at least one bonding wire.

8. The multi-chip ball grid array package of claim 5 , wherein the second active surface of the second chip faces the first surface of the laminated substrate as arranged with the second bonding pads electrically connected to the conductive connections by at least one solder bump.

9. The multi-chip ball grid array package of claim 5 further comprising an underfill disposed between the second active surface of the second chip and the first surface of the laminated substrate.

10. The multi-chip ball grid array package of claim 5 , wherein a surface of the heat sink is thermally coupled with the first back surface of the first chip, and another surface of the heat sink is not enveloped by the encapsulant, and hence is exposed.

11. The multi-chip ball grid array package of claim 10 , wherein the multi-chip ball grid array package is applicable for affixation on a printed circuit board, the printed circuit board comprises a plurality of conductive areas with the solder balls electrically connected to the conductive areas, and the exposed surface of the heat sink is thermally coupled with the conductive areas.