A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: (a) memory cells; (b) a sense amplifier connected with the memory cells via a set of signal lines having at least a first data line, the sense amplifier selectively sensing a value on the data line; and (c) a discharging circuit connected with the set of signal lines, the discharging circuit presetting the first data line to a first voltage level then discharging the first data line to a second voltage level before the sense amplifier sensing the value on the data line for a read operation, the first voltage level being greater than the second voltage level.
2. The circuit as recited in claim 1 , wherein the first voltage is substantially equal to a supply voltage level.
3. The circuit as recited in claim 1 , wherein the first voltage is less than a supply voltage level.
4. The circuit as recited in claim 1 , wherein the memory cells are low voltage memory cells, and wherein a supply voltage is applied to the semiconductor device.
5. The circuit as recited in claim 4 , wherein the supply voltage is less than 1.9 volts.
6. The circuit as recited in claim 1 , wherein the discharging circuit comprises an N-type transistor discharging circuit.
7. The circuit as recited in claim 1 , wherein the second voltage level is less than 40 percent of the first voltage level.
8. The circuit as recited in claim 1 , wherein the first data line is a bit line.
9. The circuit as recited in claim 8 , wherein the memory cells comprise SRAM memory cells.
10. A method of discharging on a data line to a desired voltage level in a low power memory device, comprising: presetting the data line to a higher voltage level; and discharging the data line from the higher voltage level to approximately the desired voltage level prior to sensing the data line for a read operation, wherein the higher voltage level is greater than the desired voltage level.
11. The method as recited in claim 10 , wherein the discharging comprises presetting the data line to approximate a supply voltage.
12. The method as recited in claim 11 , wherein the discharging comprises discharging the data line to less than 50 percent of the higher voltage.
13. The method as recited in claim 12 , wherein the discharging comprises discharging the data line with an N-type transistor discharging circuit.
14. A semiconductor memory device, comprising: (a) a memory array comprising word lines, bit lines, and memory cells wherein the word lines and the bit lines intersect and the memory cells are located at the intersections of the word lines and the bit lines; (b) a first means for sense amplifying a signal from the memory array corresponding to a state of a memory cell; (c) a second means for selectively coupling a bit line to the first means; and (d) a third means for establishing a voltage level on the bit line coupled to the first means by presetting the bit line to a first voltage level then discharging the bit line to a second voltage level before the first means senses the signal on the bit line for a road operation, the first voltage level being greater than the second voltage level.
15. The device as recited in claim 14 , wherein the first voltage level is within 10 percent of a supply voltage level.
16. The device as recited in claim 15 , wherein the second voltage level is less than 60 percent of the first voltage.
17. The device as recited in claim 14 , wherein the second means comprises a row decoder means and a column decoder means.
18. The device as recited in claim 14 , wherein the third means comprises an N-type transistor discharging circuit.
19. The device as recited in claim 17 , wherein the first and second voltage levels are selectable.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 27, 2000
January 14, 2003
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