A nonvolatile semiconductor memory device comprising a plurality of memory cells each having a transistor including a floating gate electrode as a constituent are arranged on a silicon substrate in a matrix, wherein bit lines have hierarchical structures and comprise at least a main bit line 1 and a sub-bit line 2, and a plurality of sub-bit line selection transistors 4 provided between the main bit line 1 and sub-bit line 2 which transistor 4 are respectively selectively activated depending on given row address lines, wherein a voltage applied to each gate electrode of the sub-bit line selection transistor 4 which is selected and activated when data is erased from or written on each memory cell is rendered the same as that applied to each gate electrode of the sub-bit line selection transistor 4 which becomes non-activated when not selected.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nonvolatile semiconductor memory device comprising: a plurality of memory cells each comprising a first transistor having a first electrode, a second electrode, a gate electrode and a floating gate electrode located between the gate electrode and a first gate oxide film; a plurality of first data lines each connected to the first electrode of the first transistor; a second data line; a decoder for generating a plurality of selection signals having voltage levels respectively determined in response to address information; and a plurality of second transistors each having a third electrode electrically connected to one of the first data lines, a fourth electrode electrically connected to the second data line, a gate electrode to which one of the selection signals is inputted, and a second gate oxide film, the second transistor being used to access the memory cells; wherein the selection signals have a predetermined voltage level when a high voltage level, which is higher than a power supply voltage level, is applied to a selected gate electrode of the memory cell and wherein the gate electrode of each of the second transistors has a first layer formed with the same material to that of the gate electrode of the first transistor, and a second layer formed with the same material to that of the floating gate electrode of the first transistor, the first layer being electrically connected to the second layer.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein the first gate oxide film of the first transistor and the second gate oxide film of the second transistor are respectively formed in the same process.
3. The nonvolatile semiconductor memory device according to claim 1 , wherein the second transistor comprises, a first silicon film provided on the second gate oxide film, an insulating film provided on the first silicon film, and a second silicon film provided on the insulating film and electrically connected to the first silicon film through a contact hole provided on the insulating film.
4. The nonvolatile semiconductor memory device according to claim 1 , wherein the decoder comprises: a plurality of logical circuits to which the address information and mode signals are inputted, each logical circuit outputting an output signal having a low or high voltage level in response to the address information when the voltage level of the mode signal is the low voltage level, and outputting the output signal having the high voltage level when the voltage level of the mode signal is a high voltage level; and a plurality of level shifters to which the output signals are inputted, each level shifter outputting the selection signal having a voltage level that is the same as or lower than a ground voltage when the voltage level of the output signal is the low voltage level, and outputting the selection signal having a voltage level that is the same as or higher than the power supply voltage when the voltage level of the output signal is the high voltage level.
5. The nonvolatile semiconductor memory device according to claim 1 , wherein the predetermined voltage is the same as a substrate voltage of the second transistor when data is erased from the memory cells.
6. A nonvolatile semiconductor memory device comprising: a plurality of memory cells each comprising a first transistor having a first electrode, a second electrode, a gate electrode and a floating gate electrode between the gate electrode and a gate oxide film; a plurality of first data lines each connected to the first electrode of the first transistor; a second data line; a decoder for generating a plurality of selection signals having voltage levels respectively determined in response to address information; and a plurality of second transistors each having a third electrode electrically connected to one of the first data lines, a fourth electrode electrically connected to the second data line, and a gate electrode to which one of the selection signals is inputted, the second transistor being used to access the memory cells, wherein a voltage level applied to the gate electrode and the third electrode of the second transistor is the same to that applied to a substrate on which the second transistor is formed when a high voltage, which is higher than a power supply voltage, is applied to the gate electrode of the first transistor and wherein the gate electrode of each of the second transistors has a first layer formed with the same material to that of the gate electrode of the first transistor, and a second layer formed with the same material to that of the floating gate electrode of the first transistor, the first layer being electrically connected to the second layer.
7. The nonvolatile semiconductor memory device according to claim 6 , wherein the first gate oxide film of the first transistor and the second gate oxide film of the second transistor are respectively formed in the same process.
8. The nonvolatile semiconductor memory device according to claim 6 , wherein the second transistor comprises, a first silicon film provided on the second gate oxide film, an insulating film provided on the first silicon film, and a second silicon film provided on the insulating film and electrically connected to the first silicon film through a contact hole provided on the insulating film.
9. The nonvolatile semiconductor memory device according to claim 6 , wherein the decoder comprises: a plurality of logical circuits to which the address information and mode signals are inputted, each logical circuit outputting an output signal having a low or high voltage level in response to the address information when the voltage level of the mode signal is the low voltage level, and outputting the output signal having the high voltage level when the voltage level of the mode signal is a high voltage level; and a plurality of level shifters to which the output signals are inputted, each level shifter outputting the selection signal having a voltage level that is the same as or lower than a ground voltage when the voltage level of the output signal is the low voltage level, and outputting the selection signal having a voltage level that is the same as or higher than the power supply voltage when the voltage level of the output signal is the high voltage level.
10. The nonvolatile semiconductor memory device according to claim 6 , wherein the predetermined voltage is the same as a substrate voltage of the second transistor when data is erased from the memory cells.
11. A nonvolatile semiconductor memory device comprising: a plurality of memory cells each comprising a first transistor having a first electrode, a second electrode, a gate electrode and a floating gate electrode located between the gate electrode and a first gate oxide film; a plurality of first data lines each connected to the first electrode of the first transistor; a second data line; a decoder for generating a plurality of selection signals having voltage levels respectively determined in response to address information; and a plurality of second transistors each having a third electrode electrically connected to one of the first data lines, a fourth electrode electrically connected to the second data line, a gate electrode to which one of the selection signals is inputted, and a second gate oxide film, the second transistor being used to access the memory cells; wherein the selection signals have a predetermined voltage level when a high voltage level, which is higher than a power supply voltage level, is applied to a selected gate electrode of the memory cell and wherein the first and second transistors are formed by the same process steps so that the gate electrode of the second transistor has a first layer and a second layer electrically connected to the first layer.
12. The nonvolatile semiconductor memory device according to claim 11 , wherein the second transistor comprises, a first silicon film provided on the second gate oxide film, an insulating film provided on the first silicon film, and a second silicon film provided on the insulating film and electrically connected to the first silicon film through a contact hole provided on the insulating film.
13. The nonvolatile semiconductor memory device according to claim 11 , wherein the decoder comprises: a plurality of logical circuits to which the address information and mode signals are inputted, each logical circuit outputting an output signal having a low or high voltage level in response to the address information when the voltage level of the mode signal is the low voltage level, and outputting the output signal having the high voltage level when the voltage level of the mode signal is a high voltage level; and a plurality of level shifters to which the output signals are inputted, each level shifter outputting the selection signal having a voltage level that is the same as or lower than a ground voltage when the voltage level of the output signal is the low voltage level, and outputting the selection signal having a voltage level that is the same as or higher than the power supply voltage when the voltage level of the output signal is the high voltage level.
14. The nonvolatile semiconductor memory device according to claim 11 , wherein the predetermined voltage is the same as a substrate voltage of the second transistor when data is erased from the memory cells.
15. A nonvolatile semiconductor memory device comprising: a plurality of memory cells each comprising a first transistor having a first electrode, a second electrode, a gate electrode and a floating gate electrode between the gate electrode and a gate oxide film; a plurality of first data lines each connected to the first electrode of the first transistor; a second data line; a decoder for generating a plurality of selection signals having voltage levels respectively determined in response to address information; and a plurality of second transistors each having a third electrode electrically connected to one of the first data lines, a fourth electrode electrically connected to the second data line, and a gate electrode to which one of the selection signals is inputted, the second transistor being used to access the memory cells; wherein a voltage level applied to the gate electrode and the third electrode of the second transistor is the same to that applied to a substrate on which the second transistor is formed when a high voltage, which is higher than a power supply voltage, is applied to the gate electrode of the first transistor and wherein the first and second transistors are formed by the same process steps so that the gate electrodes of the second transistor has a first layer and a second layer electrically connected to the first layer.
16. The nonvolatile semiconductor memory device according to claim 15 , wherein the second transistor comprises, a first silicon film provided on the second gate oxide film, an insulating film provided on the first silicon film, and a second silicon film provided on the insulating film and electrically connected to the first silicon film through a contact hole provided on the insulating film.
17. The nonvolatile semiconductor memory device according to claim 15 , wherein the decoder comprises: a plurality of logical circuits to which the address information and mode signals are inputted, each logical circuit outputting an output signal having a low or high voltage level in response to the address information when the voltage level of the mode signal is the low voltage level, and outputting the output signal having the high voltage level when the voltage level of the mode signal is a high voltage level; and a plurality of level shifters to which the output signals are inputted, each level shifter outputting the selection signal having a voltage level that is the same as or lower than a ground voltage when the voltage level of the output signal is the low voltage level, and outputting the selection signal having a voltage level that is the same as or higher than the power supply voltage when the voltage level of the output signal is the high voltage level.
18. The nonvolatile semiconductor memory device according to claim 15 , wherein the predetermined voltage is the same as a substrate voltage of the second transistor when data is erased from the memory cells.
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August 6, 2001
January 28, 2003
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