Method and system for pixel clock recovery

1. A method of adjusting the phase of a pixel clock comprising: receiving a first analog video frame signal having a plurality of active video portions; converting each of the active video portions of the analog video frame signal to a first plurality of pixel values in response to a pixel clock, the pixel clock having a period and having a phase relative to the active video portion; determining a first image coordinate using the first plurality of pixel values; decrementing the phase of the pixel clock by a first predetermined value; receiving a subsequent analog video frame signal having a plurality of active video portions; converting each of the active video portions of the subsequent analog video frame signal to a subsequent plurality of pixel values in response to the step of decrementing the phase of the pixel clock; determining a subsequent image coordinate using the subsequent plurality of pixel values; comparing the first image coordinate and the subsequent image coordinate; repeating the steps of decrementing the phase of the pixel clock, receiving a subsequent analog video frame signal, converting each of the active video portions of the subsequent analog video frame signal, and determining a subsequent image coordinate if the first image coordinate equals the subsequent image coordinate; and adjusting the phase of the pixel clock by a second predetermined value if the first image coordinate does not equal the subsequent image coordinate.

2. The method of claim 1 wherein each of the first analog video signal and the subsequent analog video signal has a plurality of frames, each of the plurality of frames having a plurality of horizontal sync pulses.

3. The method of claim 2 wherein each of the plurality of horizontal sync pulses precedes a respective active video portion.

4. The method of claim 1 wherein the second predetermined value is one half the period of the pixel clock.

5. A system for generating a pixel clock comprising: an analog-to-digital converter having a first converter input to receive an analog video signal having an active video portion, a second converter input and a converter output; an edge detection module having an input in communication with the output of the analog-to-digital converter and an output to provide edge coordinates; a processor having a first processor input in communication with the output of the edge detection module, a second processor input, a first processor output and a second processor output, the processor generating a frequency multiplier signal at the first processor output, the processor generating a pixel number signal indicative of the number of pixels in the active video portion at the second processor output; a comparator having a first comparator input in communication with the second processor output, a second comparator input to receive a signal indicative of a reference number of pixels and a comparator output in communication with the second processor input, the comparator generating a comparator output signal responsive to the pixel number signal and the reference number of pixels; and a clock generator having a first clock generator input in communication with the first output of the processor, a second clock generator input to receive a horizontal sync and a clock generator output in communication with the second converter input, the clock generator providing a pixel clock at the clock generator output in response to the frequency multiplier signal and the horizontal sync.

6. The system of claim 5 further comprising a controller module having a controller input in communication with the clock generator output to receive the pixel clock and a controller output, the controller module providing a display control signal at the controller output in response to the pixel clock.

7. The system of claim 5 wherein the processor comprises a phase shifter, the phase shifter adjusting the phase of the pixel clock with respect to the active video portion of the analog video signal.

8. A system for adjusting the phase of a pixel clock comprising: an analog-to-digital converter having a first converter input to receive an analog video signal having a plurality of video frames, a second converter input and a converter output to provide pixel data; an edge detection module having an input in communication with the output of the analog-to-digital converter and an output to provide edge coordinates; a processor having a first processor input in communication with the output of the edge detection module, a second processor input and a processor output to provide a phase control signal; a memory module having a memory input in communication with the output of the edge detection module and a memory output in communication with the second processor input, the memory module providing an edge coordinate from a prior video frame at the memory output; and a phase adjuster having a first input in communication with the processor output, a second input to receive the pixel clock, and an output in communication with the second converter input, the phase adjuster providing a phase-adjusted pixel clock at the output of the phase adjuster in response to the phase control signal and the pixel clock.

9. The system of claim 8 wherein the phase adjuster generates a phase-adjusted pixel clock having a phase difference with respect to the pixel clock of one half the period of the pixel clock if the current image coordinate does not equal the prior image coordinate.