A method and device for providing a gate blocking material. Specifically, a method for molding a substrate having known good and bad sites thereon, by blocking the gate area of the bad sites during the molding process. A blocking material or an injection pin are used to interrupt the flow of molding compound through an injection molding system, and thereby prevent molding compound from flowing onto the known bad substrate sites.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of molding a substrate comprising the acts of: (a) providing a substrate having a plurality of sites, each site having a gate area and being configured to receive an integrated circuit device; (b) testing the substrate to identify bad sites and good sites; (c) disposing a material on the gate area of each bad site; (d) disposing an integrated circuit device on each of any good site; (e) disposing the substrate onto a molding apparatus; (f) injecting a molding compound through a runner in the molding apparatus; and (g) disposing the molding compound on only the good sites.
2. The method, as set forth in claim 1 , wherein act (a) comprises providing a board-on-chip substrate.
3. The method, as set forth in claim 1 , wherein act (a) comprises providing a chip-on-board substrate.
4. The method, as set forth in claim 1 , wherein act (a) comprises providing a flip chip substrate.
5. The method, as set forth in claim 1 , wherein act (d) comprises disposing a memory device on each good site.
6. The method, as set forth in claim 1 , wherein act (c) comprises disposing an adhesive tape on the gate area.
7. The method, as set forth in claim 1 , wherein act (c) comprises inserting a blocking pin in the gate area.
8. The method, as set forth in claim 1 , wherein act (f) comprises injecting a resin through a runner in the molding apparatus.
9. A method of molding a substrate comprising the acts of: (a) providing a substrate having a plurality of sites, each site having a gate area and being configured to receive an integrated circuit device; (b) testing the substrate to identify bad sites and good sites; (c) disposing an integrated circuit device on each of any good site; (d) disposing the substrate onto a molding apparatus; (e) inserting blocking pins on the gate area of each bad site; (f) injecting a molding compound through a inner in the molding apparatus; and (g) disposing the molding compound on only the good sites.
10. The method, as set forth in claim 9 , wherein act (a) comprises providing a board-on-chip substrate.
11. The method, as set forth in claim 9 , wherein act (a) comprises providing a chip-on-board substrate.
12. The method, as set forth in claim 9 , wherein act (a) comprises providing a flip-chip substrate.
13. The method, as set forth in claim 9 , wherein act (c) comprises disposing a memory device on each good site.
14. The method, as set forth in claim 9 , wherein act (e) further comprises ejecting blocking pins from the molding apparatus and inserting the blocking pins on the gate area of each bad site.
15. A method of manufacturing a package comprising the acts of; (a) providing a substrate having a die site and a gate area; and (b) disposing a material on the gate area to block mold compound from entering the die site, wherein the material comprises a strip of adhesive tape, or a blocking pin.
16. The method, as set forth in claim 15 , wherein act (a) comprises providing a board-on-chip substrate.
17. The method, as set forth in claim 15 , wherein act (a) comprises providing a chip-on-board-substrate.
18. The method, as set forth in claim 15 , wherein act (a) comprises providing a flip-chip substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 19, 2000
February 25, 2003
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