An SOI structure with a dual thickness buried insulating layer and method of forming the same is provided. A first substrate has raised portions each with a planar top surface. A dielectric layer covers the first substrate and its raised portions. The dielectric layer has a planar top surface. A second substrate layer is formed on the planar top surface of the dielectric layer. Semiconductor elements may be formed in the second substrate layer. The semiconductor elements pertain to core circuit elements, peripheral circuits, and electrostatic discharge (EDS) circuits.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor chip comprising: a first substrate; a dielectric with a planar top surface covering said first substrate; and a second substrate formed directly on top of said planar top surface, said dielectric having thick and thin regions formed at predetermined locations between said first and second substrates, wherein said thick region is formed in a core of said chip and said thin region is formed in a periphery of said chip.
2. The semiconductor chip of claim 1 further comprising semiconductor devices formed in said second substrate.
3. A semiconductor chip, comprising: a first substrate; a dielectric with a continuous planar top surface covering said first substrate; and a second substrate formed directly on top of said planar top surface, said dielectric having thick and thin regions formed at predetermined locations between said first and second substrates; and a semiconductor device arranged in said second substrate.
4. The semiconductor chip of claim 3 wherein said semiconductor device is a transistor.
5. The semiconductor chip of claim 4 wherein the thickness of said dielectric also varies under said semiconductor device.
6. The semiconductor chip of claim 3 wherein said semiconductor device is a resistor.
7. The semiconductor chip of claim 6 wherein the thickness of said dielectric also varies under said semiconductor device.
8. The semiconductor chip of claim 3 wherein said semiconductor device is a decoupling capacitor.
9. The semiconductor chip of claim 3 wherein said semiconductor device is a polysilicon-bond diode.
10. The apparatus of claim 3 wherein said in regions are formed in a center portion of said chip and said thick region is formed around said center portion.
11. A silicon wafer, comprising: a first substrate; a dielectric with a continuous planar top surface covering said first substrate, wherein a thickness of said dielectric varies; a second substrate on said planar top surface of said dielectric, wherein said dielectric is continuous and isolates said first substrate from said second substrate; and semiconductor chips formed in said second substrate.
12. The apparatus of claim 11 wherein said first substrate has raised portions and said dielectric with said planar top surface covers said raised portions.
13. A silicon wafer, comprising: a first substrate; a dielectric with a planar top surface covering said first substrate, wherein a thickness of said dielectric varies; a second substrate on said planar top surface of said dielectric, wherein said dielectric is continuous and isolates said first substrate from said second substrate; and semiconductor chips formed in said second substrate, wherein the thickness of said dielectric varies in individual ones of said semiconductor chips.
14. A semiconductor device comprising: a first substrate having raised portions; a non-continuous first dielectric covering said first substrate, a top surface of said first dielectric being substantially co-planar with a top surface of said raised portions; a continuous second dielectric having a planar top surface and being formed directly on said top surfaces of said first dielectric and said raised portions; and a second substrate formed directly on top of said planar top surface of said second dielectric.
15. A semiconductor device comprising: a first substrate; a buried oxide, having a continuous planar top surface and thick and thin portions, formed on top of said first substrate; a second substrate on top of said planar top surface; a drain formed in said second substrate; a source formed in said second substrate; and a first gate structure formed over said second substrate between said source and said drain.
16. The semiconductor device of claim 15 wherein said channel region is of the same conductivity type as said source and said drain, but is lower doped.
17. The semiconductor device of claim 15 wherein said thin portion of said buried oxide is arranged under said first gate structure and said thick portions are arranged under said source and said drain.
18. The semiconductor device of claim 17 further comprising a second gate structure formed in said thick portion under only one of said source and said drain.
19. The semiconductor device of claim 15 wherein said thin portion is arranged under only one of said source and said drain and said thick portion is arranged under said first gate structure and the other of said source and said drain.
20. The semiconductor device of claim 19 further comprising a second gate structure formed in said thick portion of said buried oxide under said first gate structure.
21. The semiconductor device of claim 19 further comprising a second gate structure formed in said thick portion under the other of said source and said drain.
22. The semiconductor device of claim 15 wherein said thin portion is arranged under at least a part or all of said source, said drain, and said first gate structure.
23. The semiconductor device of claim 15 wherein said source and said drain are connected as an anode and a cathode.
24. The semiconductor device of claim 15 wherein said thin portion extends under the entire first gate structure and under at least a part of both of said source and said drain.
25. The semiconductor device of claim 15 wherein said thick portion extends under the entire gate structure and under at least a part of both of said source and said drain and a second gate structure is arranged in said thick portion which extends under the entire gate structure and under at least a part of both of said source and said drain.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 3, 1999
March 11, 2003
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