The invention relates to a method for operating a ferroelectric memory configuration in the VDD/2 mode. The memory configuration has a large number of memory cells which each have at least one selection transistor, one storage capacitor with an upper and a lower electrode and one short-circuiting transistor whose source-drain junction is connected in parallel with the storage capacitor. After a read or write procedure in which the memory cells are driven via respectively associated word lines and via respectively associated bit lines which are precharged in a precharge phase, the short-circuiting transistor is driven during a standby phase and in the process short-circuits the electrodes in the storage capacitor. The method is characterized in that the time of the standby phase coincides with the time of the precharge phase and, in the process, the bit lines are at a different potential with respect to that of the two electrodes of the storage capacitor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for operating a ferroelectric memory configuration in the V DD /2 mode, which comprises: providing a ferroelectric memory configuration having a plurality of memory cells which each have at least one selection transistor, one ferroelectric storage capacitor with an upper and a lower electrode, and one short-circuiting transistor having a source-drain junction connected in parallel with the storage capacitor; in a precharge phase, precharging bit lines; performing a procedure selected from the group consisting of a read procedure and a write procedure, in which at least some of the plurality of the memory cells are driven via respectively associated word lines and via respectively associated ones of the bit lines that have been precharged in the precharge phase; in a standby phase, driving the storage capacitor of at least one of the plurality of the memory cells to short-circuit the upper electrode and the lower electrode of the storage capacitor of the one of the plurality of the memory cells; performing the standby phase coincident in time with the precharge phase such that the bit line associated with the one of the plurality of the memory cells is at a different potential than that of the upper electrode and the lower electrode of the storage capacitor of the one of the plurality of the memory cells.
2. The method according to claim 1 , which comprises: after selecting the one of the plurality of the memory cells, ending an actuation phase of a corresponding short-circuiting transistor of the selected one of the plurality of the memory cells by applying a negative potential to a word line associated with the short-circuiting transistor.
3. The method according to claim 1 , which comprises: in order to short-circuit the upper electrode and the lower electrode of the storage capacitor of the one of the plurality of the memory cells, discharging the word line which is connected to a corresponding short-circuiting transistor to zero volts once again.
4. The method according to claim 1 , which comprises: connecting the upper electrode of all of the storage capacitors to a common electrode line.
5. The method according to claim 1 , which comprises: configuring the upper electrode of all of the storage capacitors such that each upper electrode can be connected to a common electrode line.
6. The method according to claim 1 , which comprises: providing a common electrode; and providing the short-circuiting transistors of each one of the plurality of the memory cells with a source and a drain that can be connected to the common electrode.
7. A ferroelectric memory configuration having a hysteresis characteristic, comprising: a plurality of memory cells which each have at least one selection transistor, one ferroelectric storage capacitor with an upper and a lower electrode, and one short-circuiting transistor having a source-drain junction connected in parallel with the storage capacitor; and word lines and bit lines associated with respective ones of said plurality of said memory cells; said plurality of said memory cells configured for precharging said bit lines in a precharge phase; said plurality of said memory cells configured for performing a procedure selected from the group consisting of a read procedure and a write procedure, in which at least some of said plurality of said memory cells are driven via respectively associated ones of said word lines and via respectively associated ones of said bit lines that have been precharged in the precharge phase; said plurality of said memory cells configured for, in a standby phase, driving said storage capacitor of at least one of said plurality of said memory cells to short-circuit said upper electrode and said lower electrode of said storage capacitor of said one of said plurality of said memory cells; said plurality of said memory cells configured for performing the standby phase coincident in time with the precharge phase such that one of said bit lines that is associated with said one of said plurality of said memory cells is at a different potential than that of said upper electrode and said lower electrode of said storage capacitor of said one of said plurality of said memory cells.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 4, 2001
March 25, 2003
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