Dram active termination control

1. A method of controlling active termination of a data line at a memory module comprising: receiving an external active termination control signal at a memory module and actively terminating memory devices of said module in response to receiving of said control signal and; disabling said control signal at said memory module for all memory devices on said module during a read operation in response to at least one signal generated at said module.

2. A method as defined in claim 1 , further comprising: generating said active termination control signal at a memory controller.

3. A method as in claim 2 wherein: said control signal is generated as a first logic state and is disabled by forcing said control signal to a second logic state.

4. A method of controlling active termination of a data line at a memory module comprising: receiving an external active termination control signal at a memory module and actively terminating memory devices of said module in response to receiving of said control signal; and disabling said control signal at said memory module for all memory devices on said module during a read operation in response to at least one signal generated at said module; wherein said memory module contains a first group of memory devices and a second group of memory devices, each group of said memory devices receiving said active termination control signal, and wherein said method further comprises disabling said active termination control signal for both groups of memory devices in response to a signal generated from the memory devices of either said first or second group during a read operation.

5. A method as in claim 4 wherein: said first and second groups of memory devices are respectively provided on first and second sides of said memory module.

6. A method of controlling an active termination device located within a memory device provided as part of a first memory group on a memory module, said method comprising: receiving an external active termination control signal having a first logic state at said memory device during at least a write operation to said memory device; and changing said received active termination control signal to a second logic state at said memory device in response to the presence of a read operation at said memory device or to a read operation at another memory device provided as part of a second memory group on said memory module; wherein, said first and second memory groups are respectively provided on first and second sides of said memory module.

7. A method for controlling active termination of a data line at a memory module comprising: receiving an external active termination control signal at a memory device and in response terminating a data path and; disabling said active termination control signal at said memory device to remove termination of said data path during a read operation in response to a signal generated by said memory device.

8. A method as in claim 7 , further comprising: generating said active termination control signal at a memory controller.

9. A method for controlling active termination of a data line at a memory module comprising: receiving an external active termination control signal at a memory device and in response terminating a data path; and disabling said active termination control signal at said memory device to remove termination of said data path during a read operation in response to a signal generated by said memory device; wherein, said memory device is provided on a memory module which contains a first group of said memory devices and a second group of said memory devices, each of said memory devices receiving said active termination control signal and, in response, terminating a data path thereat, and wherein said method further comprises disabling said active termination control signal for both groups of said memory devices in response to signals generated at memory devices of either said first or second group when a read operation is performed.

10. A method as in claim 9 wherein: said first and second groups of memory devices are respectively provided on first and second sides of said memory module.

11. A method for controlling active termination of a data line at a memory device provided on a memory module connected in a computer system, said method comprising: receiving an active termination control signal at said memory device and, in response, actively terminating said data line and; disabling said active termination control signal at said memory device in response to a signal generated by said memory device or by another memory device provided on said memory module during a read operation.

12. A method of controlling active termination of a data line at a memory device provided on a memory module connected in a computer system, said method comprising: receiving an active termination control signal at said memory device and, in response, actively terminating said data line; and disabling said active termination control signal at said memory device in response to a signal generated by said memory device or by another memory device provided on said memory module during a read operation, wherein, said memory device and said another memory device are respectively provided on first and second sides of said memory module.

13. A method of controlling active termination of a data line at a memory device provided on a memory module connected in a computer system, said method comprising: receiving an active termination control signal at said memory device and, in response, actively terminating said data line; and disabling said active termination control signal at said memory device in response to a signal generated by said memory device or by another memory device provided on said memory module during a read operation, wherein said data line is operatively connected to a first memory device of a first group of memory devices, and a second memory device of a second group of memory devices on said memory module, each of said first and second memory devices receiving said active termination control signal and, in response, terminating said data line, and wherein said method further comprises disabling said active termination control signal for said first and second memory devices in response to a signal generated at either said first or second memory devices during a read operation.

14. A method as in claim 13 wherein: said first and second groups of memory devices are respectively provided on opposite sides of a memory module.

15. An apparatus for controlling active termination of a data line at a first memory device comprising: an input line on said first memory device for receiving an active termination control signal; a data line termination circuit for terminating a data line in response to receipt of said active termination control signal; a switch provided between said input line and termination circuit for terminating receipt by said termination circuit of said active termination control signal by a signal generated by said first memory device in response to a read operation occurring at said first memory device.

16. An apparatus for controlling active termination of a data line at a first memory device comprising: an input line on said first memory device for receiving an active termination control signal; a data line termination circuit for terminating a data line in response to receipt of said active termination control signal; and a switch provided between said input line and termination circuit for terminating receipt by said termination circuit of said active termination control signal by a signal generated by said first memory device in response to a read operation occurring at said first memory device; wherein, said first memory device is provided on a memory module and said switch circuit is operative to terminate said receipt of said active termination control signal by said termination circuit by a signal generated by a second memory device on said module whenever a read operation occurs at a second memory device.

17. An apparatus as in claim 16 wherein said first and second memory devices are provided on opposite sides of said module.

18. An apparatus for controlling active termination of a data line at a memory module comprising: first and second memory devices respectively provided on opposite sides of a memory module, said first and second memory devices being connected to a common data line; an active termination circuit at each memory device for actively terminating said data line in response to receipt of an active termination control command, and; control circuitry at each said memory device for preventing termination of said active termination circuit at each memory device whenever either of said first and second memory devices is performing a read operation.

19. An apparatus as in claim 18 wherein: each said control circuit prevents said active termination control signal from being applied to said active termination circuit.

20. A memory module comprising: a first group of memory devices provided at a first side of said module; a second group of memory devices provided at a second side of said module, each memory device of said second group sharing at least one data line of a data bus with a corresponding memory device of said first group; each of said memory devices comprising: a termination circuit for terminating an associated data line during a write operation in response to an active termination control signal provided on a control signal line of said data bus, and; a control circuit responsive to a first control signal for preventing said termination circuit from terminating said associated data line, said first control signal being generated by said each memory device or by a corresponding memory device of another group whenever either performs a read operation.

21. A memory system, comprising: a plurality of memory modules, each being responsive to a respective active termination control signal, each memory module comprising: a first group of memory devices provided at a first side of said module; a second group of memory devices provided at a second side of said module, each memory device of said second group sharing at least one data line of a data bus with a corresponding memory device of said first group; each of said memory devices comprising: a termination circuit for terminating an associated data line during a write operation in response to an active termination control signal provided on a control signal line of said data bus, and; a control circuit responsive to a first control signal for preventing said termination circuit from terminating said associated data line, said first control signal being generated by said each memory device or by a corresponding memory device of another group whenever either performs a read operation.

22. A memory system, comprising: a memory controller providing a plurality of active termination control signals, said active termination control signals enabled in a first logic state and disabled in a second logic state, and; a plurality of said memory modules, each being responsive to a said respective active termination control signal, each said memory module comprising: a first group of memory devices provided at a first side of said module; a second group of memory devices provided at a second side of said module, each memory device of said second group sharing at least one data line of a data bus with a corresponding memory device of said first group; each of said memory devices comprising: a termination circuit for terminating an associated data line during a write operation in response to an active termination control signal provided on said active termination control signal input line, and; a control circuit responsive to a first control signal for preventing said termination circuit from terminating said associated data line, said control signal being generated by said each memory device or by a corresponding memory device of another group whenever either performs a read operation.

23. A memory system, comprising: a memory controller providing a respective active termination control signal per memory module, said respective active termination control signal enabled in a first logic state and disabled in a second logic state, and; a plurality of said memory modules, each being responsive to said respective active termination control signal, each memory module comprising: an active termination control signal input line; a first group of memory devices provided at a first side of said module; a second group of memory devices provided at a second side of said module, said first group and second group of memory devices within a said respective individual memory module connected to said active termination control signal input line, said first and second group of memory devices within a respective individual memory module transitioning to said first logic state simultaneously in response to a write operation occurring at said respective individual memory module; each of said memory devices comprising: a termination circuit for terminating an associated data line during a write operation in response to said first logic state received at said active termination control signal input line, and; a control circuit responsive to a first control signal for preventing said termination circuit from terminating said associated data line, said first control signal being generated by said each memory device or by a corresponding memory device of another group whenever either performs a read operation.

24. A processor system for controlling active termination of a data line at a first memory device comprising: a processor for causing issuance of an active termination control signal to a first memory device, said active termination control signal enabling active termination of a data line at said first memory device when said first memory device comprises a first logic state and disabling said active termination when in a second logic state; an input line on said first memory device for receiving an active termination control signal; a data line termination circuit for terminating a data line in response to receipt of said active termination control signal; a switch provided between said input line and termination circuit for terminating receipt by said termination circuit of said active termination control signal by a signal generated by said first memory device in response to a read operation occurring at said first memory device.

25. A processor system for controlling active termination of a data line at a first memory device comprising: a processor for causing issuance of an active termination control signal to a first memory device, said active termination control signal enabling active termination of a data line at said first memory device when said first memory device comprises a first logic state and disabling said active termination when in a second logic state; an input line on said first memory device for receiving an active termination control signal; data line termination circuit for terminating a data line in response to receipt of said active termination control signal; a switch provided between said input line and termination circuit for terminating receipt by said termination circuit of said active termination control signal by a signal generated by said first memory in response to a read operation occurring at said first memory device; wherein, said first memory device is provided in a first rank of memory on a memory module and said switch circuit is operative to terminate said receipt of said active termination control signal by said termination circuit by a signal generated by a second memory device provided in a second rank of memory on said module whenever a read operation occurs at a second memory device.

26. An processor system as in claim 25 wherein said first and second memory devices are provided on opposite sides of said module.

27. A processor system for controlling active termination of a data line at a memory module comprising: a processor causing transmission of an active termination control signal to a memory module, first and second memory devices respectively provided on opposite sides of said memory module, said first and second memory devices being connected to a common data line; an active termination circuit at each memory device for actively terminating said data line in response to receipt of an active termination control command, and; control circuitry at each said memory device for preventing termination of said active termination circuit at each memory device whenever either of said first and second memory devices is performing a read operation.

28. An processor system as in claim 27 wherein: each said control circuit prevents said active termination control signal from being applied to said active termination circuit.

29. A processor and memory module system comprising: a processor; a first group of memory devices provided at a first side of said module; a second group of memory devices provided at a second side of said module, each memory device of said second group sharing at least one data line of a data bus with a corresponding memory device of said first group; each of said memory devices comprising: a termination circuit for terminating an associated data line during a write operation in response to an active termination control signal provided on a control signal line of said data bus, and; a control circuit responsive to a first control signal for preventing said termination circuit from terminating said associated data line, said first control signal being generated by said each memory device or by a corresponding memory device of another group whenever either performs a read operation.

30. A processor and memory system, comprising: a processor for causing transmission of a plurality of active termination control signals used to control active termination at memory devices; a plurality of memory modules, each being responsive to a said respective active termination control signal, each memory module comprising: a first group of memory devices provided at a first side of said module; a second group of memory devices provided at a second side of said module, each memory device of said second group sharing at least one data line of a data bus with a corresponding memory device of said first group; each of said memory devices comprising: a termination circuit for terminating an associated data line during a write operation in response to a said respective active termination control signal provided on a control signal line of said data bus, and; a control circuit responsive to a first control signal for preventing said termination circuit from terminating said associated data line, said first control signal being generated by said each memory device or by a corresponding memory device of another group whenever either performs a read operation.