The present invention is generally directed to a system and method for fetching data from system memory to a device in communication with the system over a PCI bus, via an I/O cache. Broadly, the present invention may be viewed as a novel way to communicate certain fetching hints; namely, hints that specify certain qualities about the data that is to be fetched from the system memory. In operation, the I/O cache may use such hints to more effectively manage the data that passes through it. As simply one example, if, based upon the hints, the controller for the I/O cache knew (or assumed) that the data being fetched was ATM data, then it would also know (based upon the nature of ATM data) that precisely a forty-eight byte data payload was to be sent to the requesting device, and the I/O cache could pre-fetch precisely this amount of data (typically one or two cache lines). In accordance with one aspect of the invention, such a system includes an input/output (I/O) cache memory interposed between the system memory and the PCI bus, wherein the cache memory has internal memory space in the form of a plurality of data lines within the cache memory. The system further includes a plurality of registers for each PCI master that are configured to define fetching criteria. Finally, the system includes a register selector that is configured to select an active register among the plurality of registers, wherein fetching criteria for the device is specified by the active register.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A system for fetching data from a system memory to a device communicating over a PCI bus comprising: an input/output (I/O) cache memory interposed between the system memory and the PCI bus, the cache memory having memory space in the form of a plurality of data lines within the cache memory; a device configured to evaluate communications between the cache memory and an I/O bus and generate at least one set of pre-fetch hints based upon the evaluated communications; and memory manager means for managing the data within the memory space, the memory manager means further comprises means for evaluating the pre-fetch hints to control the management of data within the memory space.
2. The system as defined in claim 1 , wherein the memory manager means further comprises: means for evaluating a fetch request; means evaluating the pre-fetch hints, based upon the fetch request; and means for controllably pre-fetching a predetermined number of cache lines of data based upon a value of the pre-fetch hint.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 15, 1999
April 1, 2003
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