A buffering circuit of a semiconductor memory device is provided with a plurality of buffers divided into groups, comprising: a first controller for generating a first enable signal in response to a refresh signal and a clock enable signal; a second controller for generating a second enable signal in response to an auto-refresh signal and the first enable signal; a first buffer block including at least one of signal input buffers controlled by the first enable signal; and a second buffer block including at least one of signal input buffers controlled by the second enable signal. The groups of the buffers are independently assigned to their corresponding enable signals.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A buffering circuit of a semiconductor memory device, comprising: a first controller for generating a first enable signal by receiving a refresh signal and a clock enable signal; a second controller for generating a second enable signal by receiving an auto-refresh signal and the first enable signal; a first buffer block including at least one signal input buffer having an enable that is controlled by the first enable signal; and a second buffer block including at least one signal input buffer having an enable that is controlled by the second enable signal.
2. The buffering circuit according to claim 1 , wherein the first controller is set to operate in a refresh mode or in a non-refresh mode in accordance with the refresh signal, and latches and outputs the clock enable signal in the non-refresh mode and outputting a first signal regardless of the clock enable signal in the refresh mode; and wherein the second controller is set to operate either in a non-auto refresh mode or in an auto refresh in accordance with the auto refresh signal, and outputs the first enable signal during non-automatic refresh mode operation and outputting the second enable signal regardless of the first enable signal during auto-refresh mode operation.
3. The buffering circuit according to claim 2 , wherein the refresh signal is generated from a logic combination of a self-refresh signal and the auto refresh signal, and the first controller selects the refresh mode when a self-refresh mode and the auto-refresh mode are enabled, and the first and second buffer blocks are enabled with being controlled in accordance with the non-refresh mode, the auto-refresh mode, and the self-refresh mode.
4. The buffering circuit according to claim 3 , wherein the first buffer block includes a chip selection buffer which is enabled in the non-refresh mode while disabled in the refresh mode; wherein the second buffer block includes a row address strobe buffer, a column address strobe buffer, and a write enable buffer, which is disabled in the non-refresh mode and the self-refresh mode while enabled in the auto-refresh mode.
5. The buffering circuit according to claim 4 , wherein the chip selection buffer includes: a differential amplifier being enabled in response to a reverse signal of the first enable signal and amplifying an external chip selection signal; a first delay circuit for delaying an output signal of the differential amplifier; a second delay circuit for delaying the first enable signal; and a logical operator for combining output signals of the first and second delay circuits into a logical loop.
6. The buffering circuit according to claim 4 , wherein each of the row address strobe signal buffer, the column address strobe signal buffer, and the write enable buffer includes: a differential amplifier for amplifying an external command signal; and a delay circuit for delaying an output signal from the differential amplifier.
7. The buffering circuit according to claim 4 , wherein the first buffer block further includes address buffers.
8. The buffering circuit according to claim 2 , wherein the first controller comprises a latch holding the clock enable signal, and a signal selector for selecting one of an output signal of the latch and a signal generated by logically combining a self-refresh signal and an auto-refresh signal.
9. The buffering circuit according to claim 8 , wherein the signal selector is a logical operator for generating the first enable signal by logically combining the refresh signal and the output signal of the latch.
10. The buffering circuit according to claim 2 , wherein the second controller includes a signal selector, for generating an alternative one of the first and second enable signals in accordance with the auto-refresh signal.
11. The buffering circuit according to claim 10 , wherein the signal selector is a logical operator for generating the second enable signal by logically combining a reverse signal of the auto-refresh signal and the first enable signal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 22, 2001
April 8, 2003
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