Pulse width modulation waveform generating circuit

1. A pulse width modulation waveform generating circuit for generating 2 n kinds of pulse width modulation signals having different pulse widths in accordance with a digital signal of n (n is an integer equal to or more than 2) bits, comprising; oscillating signal output means for having m (m is an odd number more than 2) pieces of first inverting means connected in series to each other, each of these first inverting means outputting an oscillating signal with a phase different from each other, the output of said first inverting means at the last stage of the series connected first inverting means being fed back to the input side of the first inverting means at the initial stage of the series connected first inverting means; selecting means for selecting one of the signals in accordance with each of the output signals of said m pieces of first inverting means connected in series, based on at least partial bits of said digital signal of n bits, and pulse generating means for generating said pulse width modulation signal having a pulse width in accordance with the signal selected by said selecting means.

2. The pulse width modulation waveform generating circuit according to claim 1 , wherein said first inverting means are odd stages of inverters, and said selecting means have a multiplexer for selecting one of the signals in accordance with each output signal of said m pieces of first inverting means connected in series, based on logic of k( log 2 m) bits among said digital signal of n bits.

3. The pulse width modulation waveform generating circuit according to claim 2 , wherein said oscillating signal output means is a ring oscillator for allowing the output signal of a final stage of said first inverting means to feed back to an input side of a first stage of said first inverting means.

4. The pulse width modulation waveform generating circuit according to claim 3 , wherein said pulse generating means generates one of said pulse width modulation signals having the number as much as that of stages of said first inverter means in said ring oscillator, based on logic of said digital signal.

5. The pulse width modulation waveform generating circuit according to claim 4 , wherein said ring oscillator has a plurality of second inverting means connected to output signals of odd numbered stages among said first inverting means, and said selecting means select one of each output signal of even numbered stages of said first inverter means or each output signal of said plurality of second inverting means.

6. The pulse width modulation waveform generating circuit according to claim 4 , wherein said pulse generating means comprises a first edge detecting circuit for outputting an edge detecting pulse by detecting rising edges and falling edges of outputs of said ring oscillator, a second edge detecting circuit for outputting an edge detecting pulse by detecting rising edges and falling edges of outputs of said selecting means, and a set-reset circuit for being set at time when the edge detecting pulse is outputted from said first edge detecting circuit and being reset at time when the edge detecting pulse is outputted from said second edge detecting circuit, and said pulse width modulation signal is outputted from said set-reset circuit.

7. The pulse width modulation waveform generating circuit according to claim 4 , wherein said pulse generating means comprises a inversion/non-inversion setting circuit for setting whether or not the output of said selecting means should be reversed, and said pulse generating means generates said pulse width modulation signal having a pulse width in accordance with an output timing of the final stage of said first inverting means in said ring oscillator and an output timing of said inversion/non-inversion setting circuit.

8. The pulse width modulation waveform generating circuit according to claim 7 , wherein said pulse generating means generates said pulse width modulation signal by inverting the output of said selecting means by means of said inversion/non-inversion setting circuit when said selecting means selects the output signals of odd stages of said first inverting means, and generates said pulse width modulation signal without inverting the output of said selecting means by means of said inversion/non-inversion setting circuit when said selecting means selects the output signal of even stages of said first inverting means in said ring oscillator.

9. The pulse width modulation waveform generating circuit according to claim 4 , wherein said selecting means select the output signal of either even stages or odd stages of said first inverter means in said ring oscillator based on logic of the most significant bit of said digital signal, and select the output signal of a specific inverting means among the output signal of said selected inverting means based on logic of bits except for the most significant bit of said digital signal.

10. The pulse width modulation waveform generating circuit according to claim 9 , wherein said selecting means select one of the output signals of even numbered stages of said first inverting means by judging that the signal is delaying more than a half cycle for the output of said ring oscillator when the most significant bit of said digital signal is 1 .

11. The pulse width modulation waveform generating circuit according to claim 3 , wherein said pulse generating means generate one of said pulse width modulating signals having twice the number of stages as that of said first inverting means in said ring oscillator based on logic of said digital signal.

12. The pulse width modulation waveform generating circuit according to claim 11 , wherein said pulse generating means comprises a inversion/non-inversion setting circuit for setting whether or not the output of said selecting means should be reversed based on logic of the least significant bit of said digital signal, and said pulse generating means generates said pulse width modulation signal having a pulse width in accordance with an output timing of the final stage of said first inverting means in said ring oscillator and an output timing of said inversion/non-inversion setting circuit.

13. The pulse width modulation waveform generating circuit according to claim 12 , wherein said pulse generating means generates said pulse width modulation signal by inverting the output of said selecting means by means of said inversion/non-inversion setting circuit when said selecting means selects the output signals of odd stages of said first inverting means, and generates said pulse width modulation signal without inverting the output of said selecting means by means of said inversion/non-inversion setting circuit when said selecting means selects the output signal of even stages of said first inverting means in said ring oscillator.

14. The pulse width modulation waveform generating circuit according to claim 11 , said pulse generating means generates said pulse width modulating signal based on output signal of final stage of said first inverting means and input signals of odd numbered stages of said first inverting means in said ring oscillator when the least significant bit of said digital signal is 0 , and generates said pulse width modulating signal based on output signal of final stage of said first inverting means and input signals of even numbered stages of said first inverting means in said ring oscillator when the least significant bit of said digital signal is 1 .

15. The pulse width modulation waveform generating circuit according to claim 14 , wherein said selecting means select one of input signals of said first inverting means in said ring oscillator based on logic of the most significant bit of said digital signal, and said pulse generating means generate said pulse width modulating signal by selecting one of the output signal of final stage of said first inverting means in said ring oscillator or the most significant bit of said digital signal.

16. The pulse width modulation waveform generating circuit according to claim 3 , wherein said pulse generating means generate one of said pulse width modulating signals having fourth the number of stages as that of said first inverting means in said ring oscillator based on logic of said digital signal.

17. The pulse width modulation waveform generating circuit according to claim 16 , wherein said pulse generating means comprises a inversion/non-inversion setting circuit for setting whether or not the output of said selecting means should be reversed, and said pulse generating means generates said pulse width modulation signal having a pulse width in accordance with an output timing of the final stage of said first inverting means in said ring oscillator and an output timing of said inversion/non-inversion setting circuit.

18. The pulse width modulation waveform generating circuit according to claim 17 , wherein said pulse generating means generates said pulse width modulation signal by inverting the output of said selecting means by means of said inversion/non-inversion setting circuit when said selecting means selects the output signals of odd stages of said first inverting means, and generates said pulse width modulation signal without inverting the output of said selecting means by means of said inversion/non-inversion setting circuit when said selecting means selects the output signal of even stages of said first inverting means in said ring oscillator.

19. The pulse width modulation waveform generating circuit according to claim 16 , wherein said ring oscillator includes an logic inverting means for inputting to the first stage of said first inverter means by inverting output signal of final stage of said first inverter means, and said ring oscillator sets a signal propagation delay time of said logic inverting means to a half the signal propagation delay time by one stage of said plurality of first inverter means.

20. The pulse width modulation waveform generating circuit according to claim 19 , wherein said selecting means select one of input signals of said first inverting means in said ring oscillator based on logic except for the most significant bit and the least significant bit of said digital signals, and said pulse generating means generate said pulse width modulating signal by selecting one of the output signal of final stage of said first inverting means in said ring oscillator, output signal of said logic inverting means, and the most significant bit of said digital signal.

21. The pulse width modulation waveform generating circuit according to claim 19 , said pulse generating means generates a bit next to the least significant bit of said digital signal, output signal of said selecting means, the most significant bit of said digital signal, and output signal of said logic inverting means when the least significant bit of said digital signal is 0 , and generates said pulse width based on a bit next to the least significant bit of said digital signal, output signal of said selecting means, the most significant bit of said digital signal, and output signal of final stage of said first inverter means in said ring oscillator.

22. The pulse width modulation waveform generating circuit according to claim 2 , wherein an oscillating signal from outside is inputted to first stage of said first inverter means among m pieces of said first inverter means connected in series, and a value of said m and a signal propagation delay time of said first inverter means are set so that a phase difference between an oscillating signal inputted to first stage of said first inverter means and final stage of said first inverter means is substantially 180 .