The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between a digital device and a radio frequency device (wireless RF digital device), and the circuitry of a system including the packaged devices. Even more particularly, the present invention relates to a wireless radio frequency digital device functional pathway configuration for the interface between the wireless radio frequency digital device and a system in which the wireless radio frequency digital device is embedded.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit (IC) functional pathway configuration having connections comprising: V DD , GP 5 /OSC 1 /CLKIN, GP 4 /OSC 2 , GP 3 / MCLR/V PP , RFEN IN , CLKOUT, PS/DATA ASK , V DDRF , ANT 2 , ANT 1 , V SSRF , LF, XTAL, GP 2 /T 0 CKI, GP 1 , GP 0 and V SS .
2. The IC functional pathway configuration according to claim 1 , wherein the connections are arranged as follows:
3. The IC functional pathway configuration according to claim 1 , further having connections comprising: DATA FSK and FSK OUT .
4. The IC functional pathway configuration according to claim 3 , wherein the connections are arranged as follows:
5. A functional pathway configuration for a wireless radio frequency (RF) digital device, comprising: a plurality of bi-directional (GP 0 -GP 5 ) function input-outputs; a clock buffer and RF enable (RFEN IN ) function input; a crystal frequency divided by N (CLKOUT) output; a power select and amplitude shift keying (PS/DATA ASK ) function input; a differential antenna (ANT 1 and ANT 2 ) function outputS; and a loop filter (LF) function input-output; a crystal (XTAL) function input.
6. The functional pathway configuration according to claim 5 , wherein one of the plurality of bi-directional (GP 0 -GP 5 ) function input-outputs may be programmed as an oscillator crystal (OSC 1 ) function input.
7. The functional pathway configuration according to claim 5 , wherein one of the plurality of bi-directional (GP 0 -GP 5 ) function input-outputs may be programmed as an external clock (CLKIN) function input.
8. The functional pathway configuration according to claim 5 , wherein one of the plurality of bi-directional (GP 0 -GP 5 ) function input-outputs may be programmed as an oscillator crystal (OSC 2 ) function output.
9. The functional pathway configuration according to claim 5 , wherein one of the plurality of bi-directional (GP 0 -GP 5 ) function input-outputs may be programmed as a master clear (reset) ( MCLR) function input.
10. The functional pathway configuration according to claim 5 , wherein one of the plurality of bi-directional (GP 0 -GP 5 ) function input-outputs may be programmed as a programming voltage (V PP ) function input.
11. The functional pathway configuration according to claim 5 , wherein one of the plurality of bi-directional (GP 0 -GP 5 ) function input-outputs may be programmed as a (T 0 CKI) function input.
12. The functional pathway configuration according to claim 5 , wherein one of the plurality of bi-directional (GP 0 -GP 5 ) function input-outputs may be programmed as a serial programming clock function input.
13. The functional pathway configuration according to claim 5 , wherein one of the plurality of bi-directional (GP 0 -GP 5 ) function input-outputs may be programmed as a serial programming data function input.
14. The functional pathway configuration according to claim 5 , further comprising a frequency shift keying switch output (FSK OUT ) adapted for connection to a capacitor for shifting the frequency of an oscillator and a frequency shift keying control input (DATA FSK ) for controlling the FSKOUT output.
15. A functional pathway configuration for a digital device and a radio frequency device as follows:
16. The functional pathway configuration according to claim 15 , wherein pathway configuration function connections are arranged as follows: CONNECTION FUNCTION(S) P1 V DD P2 GP5/OSC1/CLKIN P3 GP4/OSC2 P4 GP3/ MCLR/V PP P5 RFEN IN P6 CLKOUT P7 PS/DATA ASK P8 V DDRF P9 ANT2 P10 ANT1 P11 V SSRF P12 No connection P13 LF (Loop Filter) P14 XTAL (Xtal OSC) P15 GP2/TOCKI P16 GP1 P17 GP0 P18 V SS .
17. The functional pathway configuration according to claim 15 , wherein pathway configuration function connections are arranged as follows: CONNECTION FUNCTION(S) P1 V DD P2 GP5/OSC1/CLKIN P3 GP4/OSC2 P4 GP3/ MCLR/V PP P5 XTAL (Xtal OSC) P6 RFEN IN P7 CLKOUT P8 PS/DATA ASK P9 V DDRF P10 ANT2 P11 ANT1 P12 V SSRF P13 No connection P14 LF (Loop Filter) P15 DATA FSK P16 FSK OUT P17 GP2/TOCKI P18 GP1 P19 GP0 P20 V SS .
18. A functional pathway configuration for a digital device and a radio frequency device, comprising: a first set of nine connections P 1 , P 2 , P 3 , P 4 , P 5 , P 6 , P 7 , P 8 and P 9 , wherein each of the first set of nine connections has a dedicated function(s) as follows: CONNECTION FUNCTION(S) P1 V DD P2 GP5/OSC1/CLKIN P3 GP4/OSC2 P4 GP3/ MCLR/V PP P5 RFEN IN P6 CLKOUT P7 PS/DATA ASK P8 V DDRF P9 ANT2 and; a second set of nine connections P 10 , P 11 , P 12 , P 13 , P 14 , P 15 , P 16 , P 17 and P 18 , wherein each of the second set of nine connections has a dedicated function(s) as follows: CONNECTION FUNCTION(S) P10 ANT1 P11 V SSRF P12 No connection P13 LF (Loop Filter) P14 XTAL (Xtal OSC) P15 GP2/TOCKI P16 GP1 P17 GP0 P18 V SS wherein at least one of the sets is disposed on one side of an integrated circuit package.
19. A functional pathway configuration for a digital device and a radio frequency device, comprising: a first set of ten connections P 1 , P 2 , P 3 , P 4 , P 5 , P 6 , P 7 , P 8 , P 9 and P 10 , wherein each of the first set of ten connections has a dedicated function(s) as follows: CONNECTION FUNCTION(S) P1 V DD P2 GP5/OSC1/CLKIN P3 GP4/OSC2 P4 GP3/ MCLR/V PP P5 XTAL (Xtal OSC) P6 RFEN IN P7 CLKOUT P8 PS/DATA ASK P9 V DDRF P10 ANT2 and; a second set often connections P 11 , P 12 , P 13 , P 14 , P 15 , P 16 , P 17 , P 18 , P 19 and P 20 , wherein each of the second set of ten connections has a dedicated function(s) as follows: CONNECTION FUNCTION(S) P11 ANT1 P12 V SSRF P13 No connection P14 LF (Loop Filter) P15 DATA ASK P16 FSK OUT P17 GP2/TOCKI P18 GP1 P19 GP0 P20 V SS wherein at least one of the sets is disposed on one side of an integrated circuit package.
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September 14, 2001
April 29, 2003
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