A method and apparatus that performs anticipatory rounding of intermediate results in a floating point arithmetic system while the intermediate results are being normalized is disclosed. One embodiment of the present invention includes four logic levels, implemented in N-NARY logic. In the first three logic levels, propagation information is gathered for preselected bit groups from the coarse and medium shift output of the normalizer as those results become available. In the fourth level, an incremented, normalized intermediate single-precision or double-precision mantissa result is produced by combining fine shift output bit values with propagation information for the appropriate top bit group, middle bit group, and bottom bit group. The appropriate bit groups are determined by examining the value of the fine shift select signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A rounding anticipator that operates in parallel with the normalizer in a floating point arithmetic system that includes a normalizer with a coarse shifter having a coarse shift output, a medium shifter having a medium shift output and a medium shift select signal, and a fine shifter having a fine shift output and a fine shift select signal, comprising: a first logic level, said first logic level accepts the coarse shift output from the normalizer and encodes coarse propagation information for a plurality of preselected coarse propagation bit groups; a second logic level, said second logic level derives propagation information for preselected groups of bit positions of the medium shift output of the normalizer by selectively combining said coarse propagation information from coarse propagation bit groups selected according to the value of the medium shift select signal from the normalizer; a third logic level, said third logic level derives top bit, middle bit, and bottom bit propagation information for a plurality of preselected top groups, middle groups, and bottom groups of bit positions of the medium shift output as a function of the value of the fine shift select signal by selectively combining said propagation information from said second logic level with medium shift output bit values; and a fourth logic level, said fourth logic level produces an incremented, normalized intermediate mantissa result by combining fine shift output bit values with said top bit propagation information, said middle bit propagation information, and said bottom bit propagation information for the top group of bit positions, the middle group of bit positions, and the bottom group of positions that correspond to said fine shift output bit values.
2. The rounding anticipator of claim 1 , wherein said first logic level, said second logic level, said third logic level, and said fourth logic level are implemented in N-NARY logic.
3. The rounding anticipator of claim 2 , wherein said incremented, normalized intermediate mantissa result is expressed in single precision format.
4. The rounding anticipator of claim 2 , wherein said incremented, normalized intermediate mantissa result is expressed in double precision format.
5. A rounding anticipation system that operates in parallel with a normalizer in a floating point arithmetic system, where the normalizer includes a coarse shifter having a coarse shift output, a medium shifter having a medium shift output and a medium shift select signal, and a fine shifter having a fine shift output and a fine shift select signal, comprising: a first logic level, said first logic level accepts the coarse shift output from the normalizer and encodes coarse propagation information for a plurality of preselected coarse propagation bit groups; a second logic level, said second logic level derives propagation information for preselected groups of bit positions of the medium shift output of the normalizer by selectively combining said coarse propagation information from coarse propagation bit groups selected according to the value of the medium shift select signal from the normalizer; a third logic level, said third logic level derives top bit, middle bit, and bottom bit propagation information for a plurality of preselected top groups, middle groups, and bottom groups of bit positions of the medium shift output as a function of the value of the fine shift select signal by selectively combining said propagation information from said second logic level with medium shift output bit values; and a fourth logic level, said fourth logic level produces an incremented, normalized intermediate mantissa result by combining fine shift output bit values with said top bit propagation information, said middle bit propagation information, and said bottom bit propagation information for the top group of bit positions, the middle group of bit positions, and the bottom group of positions that correspond to said fine shift output bit values.
6. The system of claim 5 , wherein said first logic level, said second logic level, said third logic level, and said fourth logic level are implemented in N-NARY logic.
7. The system of claim 6 , wherein said incremented, normalized intermediate mantissa result is expressed in single precision format.
8. The system of claim 6 , wherein said incremented, normalized intermediate mantissa result is expressed in double precision format.
9. A method of incrementing an intermediate mantissa result while it is being normalized in a floating point arithmetic system that includes a normalizer with a coarse shifter having a coarse shift output, a medium shifter having a medium shift output and a medium shift select signal, and a fine shifter having a fine shift output and a fine shift select signal, comprising: accepting the coarse shift output from the normalizer and encoding coarse propagation information for a plurality of preselected coarse propagation bit groups of said coarse shift output; deriving medium propagation information for preselected groups of bit positions of the medium shift output of the normalizer by selectively combining said coarse propagation information from coarse propagation bit groups selected according to the value of the medium shift select signal from the normalizer; deriving top bit, middle bit, and bottom bit propagation information for a plurality of preselected top groups, middle groups, and bottom groups of bit positions of the medium shift output as a function of the value of the fine shift select signal by selectively combining said medium propagation information with medium shift output bit values; and producing an incremented, normalized intermediate mantissa result by combining fine shift output bit values with said top bit propagation information, said middle bit propagation information, and said bottom bit propagation information for the top group of bit positions, the middle group of bit positions, and the bottom group of positions that correspond to said fine shift output bit values.
10. The method of claim 9 , further comprising using N-NARY logic.
11. The method of claim 10 , wherein said incremented, normalized intermediate mantissa result is expressed in single precision format.
12. The method of claim 10 , wherein said incremented, normalized intermediate mantissa result is expressed in double precision format.
13. A method of making a rounding anticipator that operates in parallel with the normalizer in a floating point arithmetic system where the normalizer includes a coarse shifter having a coarse shift output, a medium shifter having a medium shift output and a medium shift select signal, and a fine shifter having a fine shift output and a fine shift select signal, comprising: providing a first logic level that accepts the coarse shift output from the normalizer and encodes coarse propagation information for a plurality of preselected coarse propagation bit groups; providing a second logic level that derives propagation information for preselected groups of bit positions of the medium shift output of the normalizer by selectively combining said coarse propagation information from coarse propagation bit groups selected according to the value of the medium shift select signal from the normalizer; providing a third logic level that derives top bit, middle bit, and bottom bit propagation information for a plurality of preselected top groups, middle groups, and bottom groups of bit positions of the medium shift output as a function of the value of the fine shift select signal by selectively combining said propagation information from said second logic level with medium shift output bit values; and providing a fourth logic level, said fourth logic level produces an incremented, normalized intermediate mantissa result by combining fine shift output bit values with said top bit propagation information, said middle bit propagation information, and said bottom bit propagation information for the top group of bit positions, the middle group of bit positions, and the bottom group of positions that correspond to said fine shift output bit values.
14. The method of claim 13 , wherein said first logic level, said second logic level, said third logic level, and said fourth logic level are implemented in N-NARY logic.
15. The method of claim 14 , wherein said incremented, normalized intermediate mantissa result is expressed in single precision format.
16. The method of claim 14 , wherein said incremented, normalized intermediate mantissa result
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March 17, 2000
April 29, 2003
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