The memory device of a semiconductor chip is tested with a BIST circuit. The configuration and the method store the test results obtained by the BIST circuit. The test results are stored in the sense amplifiers of the memory device. In addition, it also possible for test programs for the BIST circuit to be stored in the sense amplifiers.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor configuration, comprising a semiconductor chip having a memory device with sense amplifiers, a BIST circuit for testing said semiconductor chip connected to said memory device, whereby test results of said semiconductor chip obtained by said BIST circuit are stored in said sense amplifiers of said memory device.
2. The configuration according to claim 1 , wherein said BIST circuit processes test programs and said sense amplifiers have the test programs for said BIST circuit stored therein.
3. A method of storing test results of a semiconductor chip having a memory device with sense amplifiers, the method which comprises testing the semiconductor chip with a BIST circuit to obtain test results, and storing the test results obtained with the BIST circuit in the sense amplifiers of the memory device.
4. The method according to claim 3 , wherein test programs for the BIST circuit are stored in the sense amplifiers.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 14, 1999
April 29, 2003
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