Timing signal occurrence circuit

1. A timing signal occurrence circuit, comprising: a plurality of signal output circuits configured to output a timing signal; a plurality of selecting circuits configured to select whether or not to operate the corresponding signal output circuit; and a plurality of delay elements connected in series, a calculator configured to fetch operands on an operand bus and to carry out the fetched operands, in sync with a delay clock on a delay clock line; a clock delay adjustment circuit configured to adjust delay of the delay clock on said delay clock line, and an operand delay adjustment circuit configured to adjust delay of the operands on said operand bus, wherein the respective outputs of said plurality of signal output circuits are connected to input terminals different from each other of said plurality of delay elements, said plurality of selecting circuits operates at least one of said signal output circuits, said clock delay adjustment circuit is provided with said signal output circuit configured to output said delay clock with timing different from each other, said operand delay adjustment circuit is provided with said signal output circuits configured to output the operands with timing different from each other, and each of said clock delay adjustment circuit and said operand control circuit selects either of said signal output circuit, so that said calculator fetches the operands after the operand on said operand bus is settled.

2. The timing signal occurrence circuit according to claim 1 , wherein said signal output circuits are provided in accordance with a calculator being a subject for timing adjustment, and wherein said selecting circuit selects either one of said signal output circuits based on the delay time of a critical path of said calculator.

3. The timing signal occurrence circuit according to claim 1 , wherein each of said signal output circuits has a tristate buffer configured to switch whether to output a signal from an output terminal or to set the output terminal to be high impedance state, based on logic of a control terminal, and wherein said selecting circuit switches logic of said control terminal.

4. The timing signal occurrence circuit according to claim 2 , wherein said tristate buffer comprises a dummy load.

5. The timing signal occurrence circuit according to claim 1 , wherein each of said signal output circuit has a tristate buffer configured to switch whether to output a signal from an output terminal or to set the output terminal to be high impedance state, wherein said selecting circuit switches logic of said control terminal, wherein said delay adjustment circuit adjusts the delay time based on wiring resistor and wiring capacitance of said delay clock line and said transfer buffer, and wherein said operand delay adjustment circuit adjusts the delay time based on the wiring resistance and the wiring capacitance of said operand bus and said tristate buffer.

6. The timing signal occurrence circuit according to claim 1 , further comprising a plurality of transistors connected to said delay clock line, these transistors being turned on in order to set said delay clock line to a prescribed voltage level when said delay clock is in a prescribed logic.

7. The timing signal occurrence circuit according to claim 1 , further comprising a plurality of transistors connected to said operand bus, these transistors being turned on in order to set said operand bus to a prescribed voltage level when said delay clock is in a prescribed logic.

8. The timing signal occurrence according to claim 1 further comprising a switch connected to said control terminal of said tristate buffer, wherein said tristate buffer outputs said delay clock when said switch is in a first change-over state, and becomes high impedance state when said switch is in a second change-over state.