A split sparse directory for a distributed shared memory multiprocessor system with multiple nodes, each node including a plurality of processors, each processor having an associated cache. The split sparse directory is in a memory subsystem which includes a coherence controller, a temporary state buffer and an external directory. The split sparse directory stores information concerning the cache lines in the node, with the temporary state buffer holding state information about transient cache lines and the external directory holding state information about non-transient cache lines.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data processing system comprising: a plurality of multiprocessor nodes each including a plurality of caches each capable of storing a plurality of cache line entries; a plurality of processors each connected to a respective cache; a coherence controller; and a directory for keeping track of the states of cache line entries in said plurality of caches, wherein a first part of said directory holds temporary state information about a first subset of line entries for said plurality of caches and a second part of said directory holds non-temporary state information about a second subset of line entries for said plurality of caches.
2. A data processing system as in claim 1 wherein said second part of said directory comprises at least one external directory.
3. A data processing system as in claim 1 wherein said first and second parts of said directory are physically separate.
4. A data processing system as in claim 1 wherein a cache coherence protocol within at least one of said plurality of multiprocessor nodes uses a snoopy coherence protocol and a cache coherence protocol across said plurality of multiprocessor nodes uses a directory-based cache coherence protocol.
5. A data processing system as in claim 3 wherein said first part of said directory is an internal on-chip directory and said second part of said directory is an external off-chip directory.
6. A data processing system comprising: multiple nodes each having a plurality of processors coupled to a memory bus, each processor having a respective cache storing a plurality of cache line entries; a bus interface element for coupling to said memory bus; a directory, including a first part for holding temporary state information and a second part for holding non-temporary state information of cache line entries in said caches; and a coherence controller coupled to said bus interface element and to said directory for reading state information from said directory and updating said state information.
7. A data processing system as in claim 6 wherein said second part of said directory comprises at least one external directory.
8. A data processing system as in claim 6 wherein said first and second parts of said directory are physically separate.
9. A data processing system as in claim 6 wherein a cache coherence protocol within at least one of said multiple nodes uses a snoopy coherence protocol and a cache coherence protocol across said multiple nodes uses a directory-based cache coherence protocol.
10. A data processing system as in claim 8 wherein said first part of said directory is an internal on-chip directory and said second part of said directory is an external off-chip directory.
11. A method for maintaining cache coherence in a data processing system including multiple nodes each having a plurality of processors coupled to a memory bus, each processor having a respective cache memory, comprising the steps of: storing information about cached memory locations in a directory, wherein a first part of said directory holds transient state information about a first plurality of cache line entries and a second part of said directory holds non-transient state information about a second plurality of cache line entries; and coupling a coherence controller to said cache memories for maintaining cache coherence.
12. The method of claim 11 , wherein said step of coupling comprises the steps of: reading state information from said directory; and updating said state information in said directory.
13. The method of claim 11 , further comprising the steps of: using a snoopy coherence protocol within at least one of said multiple nodes; and using a directory-based cache coherence protocol across said multiple nodes.
14. A method of maintaining cache coherency in a data processing system including a plurality of nodes and an interconnect, each node having a plurality of multiprocessors with respective caches and memory; and a directory for storing state information for a plurality of cached memory lines, wherein a first part of said directory holds transient state information about said plurality of cached memory lines and a second part of said directory holds non-transient state information about said plurality of cached memory lines, comprising the step of: receiving from a memory bus a bus request for the control of one of said cached memory lines.
15. The method of claim 14 , further comprising the steps of: using a snoopy coherence protocol within at least one of said plurality of nodes; and using a directory-based cache coherence protocol across said plurality of nodes.
16. The method of claim 14 , further comprising the steps of: reading state information from said directory; and updating said state information in said directory.
17. A data processing system including a plurality of nodes and an interconnect, each node having a plurality of multiprocessors with respective caches and memory, and a directory for storing state information for a plurality of cached memory lines, wherein one part of said directory holds transient state information about a first subset of said plurality of cached memory lines and a second part of said directory holds non-transient state information about a second subset of said plurality of cached memory lines, said data processing system also comprising: a control unit coupled to a memory bus for receiving memory bus requests.
18. A data processing system as in claim 17 wherein said second part of said directory comprises at least one external directory.
19. A data processing system as in claim 17 wherein said first and second parts of said directory are physically separate.
20. A data processing system as in claim 17 wherein said first part of said directory is an internal on-chip directory and said second part of said directory is an external off-chip directory.
21. A data processing system as in claim 17 wherein a cache coherence protocol within at least one of said plurality of nodes uses a snoopy coherence protocol and a cache coherence protocol across said plurality of nodes uses a directory-based cache coherence protocol.
22. The data processing system of claim 17 , further comprising: means for reading said state information of said cached memory lines; and means for updating said state information for said cached memory lines.
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March 30, 1999
May 6, 2003
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