A method for producing an integrated circuit wherein a substrate is provided that includes a circuit structure and a first metalization structure disposed thereover comprising at least one layer with plated holes extending therethrough and into the circuit structure. The plated holes are insulated and a planarizing layer is disposed over the metalization structure. A handling wafer is applied over the substrate permitting the substrate to be thinned such that metalized connections disposed in the plated holes are exposed. A second metalization structure is provided and connected to the circuit structure and/or the first metalization structure by the metalized connections.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for producing an integrated circuit wherein a first substrate is first provided with a circuit structure ( 1 ) and a first metalization structure ( 2 , 3 ) disposed over a first side thereof and including one or more layers with plated holes extending therethrough and into the circuit structure ( 1 ), the plated holes ( 4 ) being insulated against the circuit structure ( 1 ) and provided with metalized connections ( 5 ), a planarizing layer ( 7 ) being disposed over the first metalization structure ( 2 , 3 ), the first substrate being rebonded to a handling wafer ( 8 ), a second side opposite the first side of the first substrate being thinned so that the plated holes ( 4 ) are open and metalized connections ( 5 ) are exposed, comprising producing a second metalization structure ( 10 , 11 ) connected with the first metalization structure ( 2 , 3 ) and/or the circuit structure ( 1 ) by means of the metalized connections ( 5 ) on the second side of the circuit structure ( 1 ).
2. The method according to claim 1 , including etching alignment marks which are recognizable at least after thinning of the substrate and etched before thinning of the substrate or before rebonding to the handling wafer ( 8 ).
3. The method according to claim 2 , wherein the etching of the alignment marks is effected simultaneously with the production of the plated holes ( 4 ).
4. The method according to claim 1 , including metalizing the plated holes ( 4 ) before thinning and ending the thinning process when the metalization ( 5 ) of the metalized connections is reached.
5. The method according to claim 1 , wherein the plated holes ( 4 ) are metalized after thinning and the thinning process is ended when the plated holes ( 4 ) are reached.
6. The method according to claim 1 , wherein at least one of the first and second metalization structures ( 2 , 3 , 10 , 11 ) disposed on both sides of the circuit structure ( 1 ) has at least one metalization level serving as an intrusion detection screen.
7. The method according to claim 1 , wherein the first substrate has a buried oxide layer ( 22 ) with an insulating effect, and a circuit structure ( 23 ) connected with the metalization structures disposed on both sides is provided at least on one side of the oxide layer.
8. The method according to claim 7 , wherein a second circuit structure ( 27 ) is produced on the other side of the oxide layer ( 22 ) after rebonding to a first handling wafer ( 20 ) and thinning of the first substrate.
9. The method according to claim 8 , wherein the backside is processed with a metalization structure ( 10 , 11 , 28 , 29 ) and planarized.
10. The method according to claim 7 , wherein the first substrate is rebonded to a second handling wafer ( 30 ) and the first circuit structure ( 23 ) is provided with a metalization structure.
11. The method according to claim 7 , wherein the plated-through holes ( 25 ) are etched through and metalized before rebonding to the first handling wafer ( 20 ).
12. The method according to claim 1 , wherein the wafer processed on both sides is connected with one or more further wafers processed on one or both sides to form a chip stack.
13. An integrated circuit with a substrate including a circuit structure ( 1 ) and a first metalization structure ( 2 , 3 ) having at least one metalization layer and disposed over a first side of the circuit structure ( 1 ), comprising: a second metalization structure ( 10 , 11 ) disposed over a second side of the circuit structure ( 1 ), the first and second metalization structures being connected by means of interchip connections; wherein at least one metalization layer of at least one of the first and second metalization structures is an intrusion detection screen.
14. The integrated circuit according to claim 13 , wherein the circuit structure ( 1 , 23 , 27 ) is disposed on a substrate with a buried oxide layer ( 22 ), the circuit structure being distributed over both sides of the oxide layer.
15. The integrated circuit according to claim 13 , including a chip stack formed from an integrated circuit processed on both sides which is connected with one or more further chips processed on one or both sides.
16. A smart card comprising an integrated circuit or a module according to claim 13 .
17. A module for incorporation in a smart card having an integrated circuit with a substrate including a circuit structure and a first metalization structure ( 2 , 3 ) having at least one metalization layer and disposed over a first side of the circuit structure ( 1 ), comprising: a second metalization structure ( 10 , 11 ) disposed over a second side of the circuit structure ( 1 ), the first and second metalization structures being connected by means of interchip connections; wherein at least one metalization layer of at least one of the first and second metalization structures is an intrusion detection screen.
18. The module according to claim 17 , wherein the circuit structure of the integrated circuit is disposed on a substrate with a buried oxide layer, the circuit structure being distributed over both sides of the oxide layer.
19. The module according to claim 17 , wherein the integrated circuit comprises a chip stack formed from an integrated circuit processed on both sides which is connected with one or more further chips processed on one or both sides.
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August 15, 2001
June 24, 2003
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