Test thin film transistors are provided outside of the pixel region of an LCD panel that includes an array of pixel thin film transistors and intersecting arrays of spaced apart data lines and gate lines connected to the array of pixel thin film transistors. A respective test thin film transistor is connected to a respective one of the data lines or gate lines. At least subgroups of the test thin film transistors are commonly connected to provide common energization of subgroups of data lines or test lines for gross testing of the LCD panels. Rubber pads are therefore not required to energize each individual data line or gate line for gross testing. Moreover, after testing is completed, test thin film transistors need not be cut or otherwise mechanically disconnected. Test thin film transistors may be organized for tape automated bonding (TAB) LCD panels or for chip on glass (COG) LCD panels. Associated methods are also provided.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An LCD panel comprising: a pixel region including an array of pixel thin film transistors and intersecting arrays of spaced apart data lines and gate lines connected to the array of pixel thin film transistors; and a plurality of test thin film transistors outside the pixel region, each test thin film transistor including a source, a drain and a gate, one of the source and drain of a respective test thin film transistor being connected to a respective one of the data lines or gate lines, the other of the sources and drains of the test thin film transistors being commonly connected and the gates of the test thin film transistors being commonly connected.
2. An LCD panel according to claim 1 wherein the drain of a respective test thin film transistor is connected to a respective one of the gate lines, the sources of the test thin film transistors are commonly connected and the gates of the test thin film transistors are commonly connected.
3. An LCD panel according to claim 2 wherein each of the gate lines includes first and second ends, and wherein the drain of a respective test thin film transistor is connected to the first end of a respective one of the gate lines.
4. An LCD panel according to claim 3 wherein each of the gate lines includes a bonding pad at the first end thereof, and wherein the drain of a respective test thin film transistor is connected to the bonding pad at the first end of a respective one of the gate lines.
5. An LCD panel according to claim 4 wherein the bonding pads are arranged in a row at the first ends of the gate lines for tape automated bonding of gate driver chips thereto.
6. An LCD panel according to claim 4 wherein the bonding pads are arranged in multi-sided groups at the first ends of the gate lines for chip on glass mounting of gate driver chips thereto.
7. An LCD panel according to claim 3 wherein each of the gate lines includes a bonding pad at the first end thereof, and wherein the drain of a respective test thin film transistor is connected to the second end of a respective one of the gate lines.
8. An LCD panel according to claim 2 further comprising a first gate probe contact and a second gate probe contact and wherein the sources of the test thin film transistors are commonly connected to the first gate probe contact and the gates of the test thin film transistors are commonly connected to the second gate probe contact.
9. An LCD panel according to claim 8 in combination with a test fixture that energizes the first and second gate probe contacts to thereby energize the array of pixel thin film transistors for gross testing.
10. An LCD panel according to claim 1 wherein the drain of a respective test thin film transistor is connected to a respective one of the data lines, the sources of the test thin film transistors are commonly connected and the gates of the test thin film transistors are commonly connected.
11. An LCD panel according to claim 10 wherein each of the data lines includes first and second ends, and wherein the drain of a respective test thin film transistor is connected to the first end of a respective one of the data lines.
12. An LCD panel according to claim 11 wherein each of the data lines includes a bonding pad at the first end thereof, and wherein the drain of a respective test thin film transistor is connected to the bonding pad at the first end of a respective one of the data lines.
13. An LCD panel according to claim 12 wherein the bonding pads are arranged in a row at the first ends of the data lines for tape automated bonding of data driver chips thereto.
14. An LCD panel according to claim 12 wherein the bonding pads are arranged in multi-sided groups at the first ends of the data lines for chip on glass mounting of data driver chips thereto.
15. An LCD panel according to claim 11 wherein each of the data lines includes a bonding pad at the first end thereof, and wherein the drain of a respective test thin film transistor is connected to the second end of a respective one of the data lines.
16. An LCD panel according to claim 1 wherein the drain of a respective test thin film transistor is connected to a respective one of the gate lines, the sources of subgroups of the test thin film transistors are commonly connected to provide a plurality of common source connections and the gates of subgroups of the test thin film transistors are commonly connected to provide a plurality of common gate connections.
17. An LCD panel according to claim 16 further comprising a plurality of first gate probe contacts and a plurality of second gate probe contacts wherein the sources of subgroups of the test thin film transistors are commonly connected to a respective one of the first gate probe contacts to provide a plurality of common source connections and the gates of subgroups of the test thin film transistors are commonly connected to a respective one of the second gate probe contacts to provide a plurality of common gate connections.
18. An LCD panel according to claim 17 in combination with a test fixture that energizes the plurality of first and second gate probe contacts to thereby energize the array of pixel thin film transistors for gross testing.
19. An LCD panel according to claim 1 wherein the drain of a respective test thin film transistor is connected to a respective one of the data lines, the sources of subgroups of the test thin film transistors are commonly connected to provide a plurality of common source connections and the gates of subgroups of the test thin film transistors are commonly connected to provide a plurality of common gate connections.
20. An LCD panel according to claim 10 further comprising a first data probe contact and a second data probe contact and wherein the sources of the test thin film transistors are commonly connected to the first data probe contact and the gates of the test thin film transistors are commonly connected to the second data probe contact.
21. An LCD panel according to claim 20 in combination with a test fixture that energizes the first and second data probe contacts to thereby energize the array of pixel thin film transistors for gross testing.
22. An LCD panel according to claim 19 further comprising a plurality of first data probe contacts and a plurality of second data probe contacts wherein the sources of subgroups of the test thin film transistors are commonly connected to a respective one of the first data probe contacts to provide a plurality of common source connections and the gates of subgroups of the test thin film transistors are commonly connected to a respective one of the second data probe contacts to provide a plurality of common gate connections.
23. An LCD panel according to claim 22 in combination with a test fixture that energizes the plurality of first and second data probe contacts to thereby energize the array of pixel thin film transistors for gross testing.
24. A method of gross testing an LCD panel comprising a pixel region including an array of pixel thin film transistors and intersecting arrays of spaced apart data lines and gate lines connected to the array of pixel thin film transistors, the testing method comprising the steps of: fabricating a plurality of test thin film transistors outside the pixel region, each test thin film transistor including a source, a drain and a gate, one of the source and drain of a respective test thin film transistor being connected to a respective one of the data lines or gate lines, the other of the sources and drains of the test thin film transistors being commonly connected and the gates of the test thin film transistors being commonly connected; and energizing the commonly connected other of the sources and drains of the test thin film transistors and the commonly connected gates of the pixel thin film transistors to thereby energize the array of pixel thin film transistors and provide gross testing of the LCD panel.
25. A method according to claim 24 : wherein the drain of a respective test thin film transistor is connected to a respective one of the gate lines, the sources of the test thin film transistors are commonly connected and the gates of the test thin film transistors are commonly connected; and wherein the energizing step comprises the step of energizing the commonly connected sources and the commonly connected gates.
26. A method according to claim 25 : wherein the fabricating step further comprises the step of fabricating a first gate probe contact and a second gate probe contact, wherein the sources of the test thin film transistors are commonly connected to the first gate probe contact and the gates of the test thin film transistors are commonly connected to the second gate probe contact; and wherein the energizing step comprises the step of energizing the first gate probe contact and the second gate probe contact.
27. A method according to claim 26 wherein the energizing step is performed by a test fixture including first and second gate probes at locations corresponding to the first and second gate probe contacts to thereby energize the array of pixel thin film transistors for gross testing.
28. A method according to claim 24 : wherein the drain of a respective test thin film transistor is connected to a respective one of the data lines, the sources of the test thin film transistors are commonly connected and the gates of the test thin film transistors are commonly connected; and wherein the energizing step comprises the step of energizing the commonly connected sources and the commonly connected gates.
29. A method according to claim 28 : wherein the fabricating step further comprises the step of fabricating a first data probe contact and a second data probe contact, wherein the sources of the test thin film transistors are commonly connected to the first data probe contact and the gates of the test thin film transistors are commonly connected to the second data probe contact; and wherein the energizing step comprises the step of energizing the first data probe contact and the second data probe contact.
30. A method according to claim 29 wherein the energizing step is performed by a test fixture including first and second data probes at locations corresponding to the first and second data probe contacts to thereby energize the array of pixel thin film transistors for gross testing.
31. A method according to claim 24 : wherein the drain of a respective test thin film transistor is connected to a respective one of the gate lines, the sources of subgroups of the test thin film transistors are commonly connected to provide a plurality of common source connections and the gates of subgroups of the test thin film transistors are commonly connected to provide a plurality of common gate connections; and wherein the energizing step comprises the step of energizing the common source connections and the common gate connections.
32. A method according to claim 31 : wherein the fabricating step further comprises the step of fabricating a plurality of first gate probe contacts and a plurality of second gate probe contacts wherein the sources of subgroups of the test thin film transistors are commonly connected to a respective one of the first gate probe contacts to provide a plurality of common source connections and the gates of subgroups of the test thin film transistors are commonly connected to a respective one of the second gate probe contacts to provide a plurality of common gate connections; and wherein the energizing step comprises the step of energizing the plurality of first gate probe contacts and the plurality of second gate probe contacts.
33. A method according to claim 32 wherein the energizing step is performed by a test fixture including a plurality of first and second gate probes at locations corresponding to the plurality of first and second gate probe contacts to thereby energize the array of pixel thin film transistors for gross testing.
34. A method according to claim 24 : wherein the drain of a respective test thin film transistor is connected to a respective one of the data lines, the sources of subgroups of the test thin film transistors are commonly connected to provide a plurality of common source connections and the gates of subgroups of the test thin film transistors are commonly connected to provide a plurality of common gate connections; and wherein the energizing step comprises the step of energizing the common source connections and the common gate connections.
35. A method according to claim 34 : wherein the fabricating step further comprises the step of fabricating a plurality of first data probe contacts and a plurality of second data probe contacts wherein the sources of subgroups of the test thin film transistors are commonly connected to a respective one of the first data probe contacts to provide a plurality of common source connections and the gates of subgroups of the test thin film transistors are commonly connected to a respective one of the second data probe contacts to provide a plurality of common gate connections; and wherein the energizing step comprises the step of energizing the plurality of first data probe contacts and the plurality of second data probe contacts.
36. A method according to claim 35 wherein the energizing step is performed by a test fixture including a plurality of first and second data probes at locations corresponding to the plurality of first and second data probe contacts to thereby energize the array of pixel thin film transistors for gross testing.
37. A method according to claim 24 wherein the energizing step is performed by a test fixture.
38. A method according to claim 24 wherein the array of pixel thin film transistors and the plurality of test thin film transistors are fabricated simultaneously.
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October 24, 1997
July 8, 2003
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