In a data carrier (1) with a chip module (3), the chip (5) of the chip module (3) is provided, in the region of its chip connecting layers (8), with a respective wire connecting means which is formed by a flat metal layer (10) and whereto an end (13), bonded in a wedge-shape fashion, of a bond wire (11) is connected.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A chip module ( 3 ) with a holder means ( 4 ) and with a chip ( 5 ) connected to the holder means ( 4 ), where the chip ( 5 ) has at least one chip connecting layer ( 8 ), and where the holder means ( 4 ) has at least one holder means connecting layer ( 9 ), and where an associated wire connecting means ( 10 ) is provided on the chip connecting layer ( 8 ), and where the wire connecting means ( 10 ) and the holder means connecting layer ( 9 ) are connected to one another with the aid of a bond wire ( 11 ), and where the bond wire ( 11 ) has a bonded first end ( 12 ) and a second end ( 13 ) bonded in a wedge-shape fashion, and where the bonded first end ( 12 ) is connected to the holder means connecting layer ( 9 ) and the second end ( 13 ) bonded in a wedge-shape fashion is connected to the wire connecting means ( 10 ), and where a flat metal layer ( 10 ) extending parallel to the chip connecting layer ( 8 ) is provided as the wire connecting means ( 10 ), said flat metal layer ( 10 ) comprising a straight wall bump.
2. A chip module ( 3 ) as claimed in claim 1 , where the flat metal layer ( 10 ) provided on the chip connecting layer ( 8 ) covers the chip connecting layer ( 8 ) entirely.
3. A chip module ( 3 ) as claimed in claim 1 , where the flat metal layer ( 10 ) consists of gold.
4. A data carrier ( 1 ) with a chip module ( 3 ) with a holder means ( 4 ) and with a chip ( 5 ) connected to the holder means ( 4 ), where the chip ( 5 ) has at least one chip connecting layer ( 8 ), and where the holder means ( 4 ) has at least one holder means connecting layer ( 9 ), and where an associated wire connecting means ( 10 ) is provided on the chip connecting layer ( 8 ), and where the wire connecting means ( 10 ) and the holder means connecting layer ( 9 ) are connected to one another with the aid of a bond wire ( 11 ), and where the bond wire ( 11 ) has a bonded first end ( 12 ) and a second end ( 13 ) bonded in a wedge-shape fashion, and where the bonded firs end ( 12 ) is connected to the holder means connecting layer ( 9 ) and the second end ( 13 ) bonded in a wedge-shape fashion is connected to the wire connecting means ( 10 ), and where a flat metal layer ( 10 ) extending parallel to the chip connecting layer ( 8 ) is provided as the wire connecting means ( 10 ), said flat metal layer ( 10 ) comprising a straight wall bump.
5. A data carrier ( 1 ) as claimed in claim 4 , where the flat metal layer ( 10 ) provided on the chip connecting layer ( 8 ) covers the chip connecting layer ( 8 ) entirely.
6. A data carrier ( 1 ) as claimed in claim 4 , where the flat metal layer ( 10 ) consists of gold.
7. A chip module ( 3 ) as claimed in claim 1 , wherein the straight wall bump ( 10 ) has a thickness in a range of between 01.0 and 18.0 m.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 15, 2002
July 15, 2003
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