A dual mode high voltage power supply circuit using an external high voltage connected through an internal high voltage switch which determines whether the memory blocks of a non-volatile memory circuit are programmed in a first mode from an internal high voltage charge pump or are programmed in a second mode from an external high voltage power supply connected in parallel to the internal high voltage charge pump. When the dual mode high voltage power supply circuit is operating in the first mode using only its internal change pump high voltage, it operates in a low power, low-speed mode, programming only one or two bits at a time but allowing the charge pump area on the die to be small. When operating in the second mode, in which the external power supply high voltage is available, eight or more bits can be written to at the same time, thus allowing a fast programming mode without the need for increasing the size of the internal charge pump, thus eliminating the additional space and cost required to increase the die area.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A dual mode high voltage power supply circuit for providing increased speed in programming during testing of low voltage nonvolatile memories, said circuit comprising: a charge pump receiving an external power supply low voltage (V DD ) on an input and producing a programming high voltage (V M ) on an output, the charge pump having a clock input for receiving a timing signal; an external high voltage switch having a first input terminal, a second input terminal, an output terminal, and a plurality of enable inputs, said external high voltage switch receiving an external power supply high voltage (V PP ) at the first input terminal, receiving the external power supply low voltage (V DD ) at the second input terminal and producing the programming high voltage (V M ) at the output terminal, said output terminal being connected to the output of the charge pump at a common programming node, the external voltage switch being activated and deactivated by a fast program enable signal applied to a first one of the enable inputs; a plurality of nonvolatile memory blocks, each nonvolatile memory block being connected to a memory block switch having a programming input terminal connected to the common programming node to receive the programming voltage, and each memory block switch having a control input terminal for receiving a signal to activate or deactivate the memory block switch, each of the nonvolatile memory blocks being programmed with the programming voltage when its respective memory block switch is activated; a programming control circuit having an input terminal for receiving the fast program enable signal and a plurality of output terminals being connected to the control input terminals of the memory block switches; and means for generating the timing signals for the charge pump, whereby the dual mode high voltage power supply operates in a first programming mode when the external high voltage switch is deactivated and the dual mode high voltage power supply operates in a second programming mode when the external high voltage switch is activated.
2. The dual mode high voltage power supply circuit of claim 1 wherein the means for generating the timing signals includes: an oscillator circuit providing a clock signal; a divider and hysteresis comparator circuit for providing regulation of the programming voltage, the divider and hysteresis comparator circuit receiving the programming voltage on a signal input and a reference voltage on a reference input and producing an analog enable signal on an output terminal; a flip-flop circuit receiving the clock signal at a clock terminal and the analog enable signal at a data terminal and producing a timing enable signal at an output terminal; and a logic gate receiving the clock signal at a first input terminal and the timing enable signal at a second input terminal and producing the timing signals at an output terminal.
3. The dual mode high voltage power supply of claim 2 wherein the timing enable signal is supplied to a second one of the enable inputs of the external high voltage switch.
4. The dual mode high voltage power supply of claim 1 wherein the programming high voltage for programming the nonvolatile memory blocks is generated from the charge pump when the external voltage switch is deactivated.
5. The dual mode high voltage power supply of claim 4 wherein two of the nonvolatile memory blocks are programmed at the same time.
6. The dual mode high voltage power supply of claim 1 wherein the programming high voltage for programming the nonvolatile memory blocks is generated from both the external power supply high voltage and the charge pump when the external voltage switch is activated.
7. The dual mode high voltage power supply of claim 6 wherein at least eight of the nonvolatile memory blocks are programmed at the same time.
8. The dual mode high voltage power supply of claim 1 wherein the external voltage switch comprises: a diode connected to the second input terminal; a switch resistor connected to the first input terminal; a pair of PMOS transistors connected in a cross coupled manner between the diode and the switch resistor, a high voltage enable line being produced at a drain terminal of one of the pair of PMOS transistors; a first logic gate receiving the plurality of enable inputs and producing a first gate output on an output terminal; a first NMOS transistor having a drain terminal connected to the high voltage enable line, a source terminal connected to a ground potential and receiving the first gate output on a gate terminal; a second logic gate receiving the first gate output at an input terminal and producing a second gate output at an output terminal; a second NMOS transistor having a drain terminal connected to a drain terminal of the other of the pair of PMOS transistors, a source terminal connected to a ground potential and receiving the second gate output on a gate terminal; a pass transistor having a gate terminal connected to the high voltage enable line, a drain terminal connected to the second input terminal, and a source terminal connected to the output terminal; and a pass resistor connected in series between the drain of the pass transistor and the second input terminal.
9. A dual mode high voltage power supply circuit for providing increased speed in programming during testing of low voltage nonvolatile memories, said circuit comprising: an internal charge pump receiving an external power supply low voltage (V DD ) on an input and producing a programming high voltage (V M ) on an output, the charge pump having a clock input for receiving a timing signal; an external high voltage switch having a first input terminal, a second input terminal, an output terminal, and a plurality of.enable inputs, said external high voltage switch receiving an external power supply high voltage (V PP ) at the first input terminal, receiving the external power supply low voltage (V DD ) at the second input terminal and producing the programming high voltage (V M ) at the output terminal, the external high voltage switch being activated by a fast program enable signal applied to a first one of the enable inputs, the dual mode high voltage power supply operating in a first programming mode in which the programming voltage is generated from solely the charge pump when the external high voltage switch is deactivated and the dual mode high voltage power supply operating in a second programming mode in which the programming high voltage is generated from both the charge pump and the external power supply high voltage when the external high voltage switch is activated, said output terminal being connected to the output of the charge pump at a common programming node; a plurality of nonvolatile memory blocks, each nonvolatile memory block being connected to a memory block switch having a programming input terminal connected to the common programming node to receive the programming high voltage, and each memory block switch having a control input terminal for receiving a signal to activate or deactivate the memory block switch, each of the nonvolatile memory blocks being programmed with the programming high voltage when its respective memory block switch is activated; a programming control circuit having an input terminal for receiving the fast program enable signal and a plurality of output terminals being connected to the control input terminals of the memory block switches; and means for generating the timing signals for the charge pump.
10. The dual mode high voltage power supply circuit of claim 9 wherein the means for generating the timing signals includes: an oscillator circuit providing a clock signal; a divider and hysteresis comparator circuit for providing regulation of the programming high voltage, the divider and hysteresis comparator circuit receiving the programming high voltage on a signal input and a reference voltage on a reference input and producing an analog enable signal on an output terminal; a flip-flop circuit receiving the clock signal at a clock terminal and the analog enable signal at a data terminal and producing a timing enable signal at an output terminal; and a logic gate receiving the clock signal at a first input terminal and the timing enable signal at a second input terminal and producing the timing signals at an output terminal.
11. The dual mode high voltage power supply of claim 10 wherein the timing enable signal is supplied to a second one of the enable inputs of the external high voltage switch.
12. The dual mode high voltage power supply of claim 9 wherein the external high voltage switch is deactivated and two of the nonvolatile memory blocks are programmed at the same time.
13. The dual mode high voltage power supply of claim 9 wherein the external high voltage switch is activated and at least eight of the non-volatile memory blocks are programmed at the same time.
14. The dual mode high voltage power supply of claim 9 wherein the external voltage switch comprises: a diode connected to the second input terminal; a switch resistor connected to the first input terminal; a pair of PMOS transistors connected in a cross coupled manner between the diode and the switch resistor, a high voltage enable line being produced at a drain terminal of one of the pair of PMOS transistors; a first logic gate receiving the plurality of enable inputs and producing a first gate output on an output terminal; a first NMOS transistor having a drain terminal connected to the high voltage enable line, a source terminal connected to a ground potential and receiving the first gate output on a gate terminal; a second logic gate receiving the first gate output at an input terminal and producing a second gate output at an output terminal; a second NMOS transistor having a drain terminal connected to a drain terminal of the other of the pair of PMOS transistors, a source terminal connected to a ground potential and receiving the second gate output on a gate terminal; a pass transistor having a gate terminal connected to the high voltage enable line, a drain terminal connected to the second input terminal, and a source terminal connected to the output terminal; and a pass resistor connected in series between the drain of the pass transistor and the second input terminal.
15. A dual mode high voltage power supply circuit for providing increased speed in programming during testing of low voltage nonvolatile memories, said circuit comprising: a charge pump receiving an external power supply low voltage (V DD ) on an input and producing a programming high voltage (V M ) on an output, the charge pump having a clock input for receiving a timing signal; an external voltage switch having a first input terminal, a second input terminal, an output terminal, and a plurality of enable inputs, said external voltage switch receiving an external power supply voltage (V PP ) at the first input terminal, receiving the external power supply low voltage (V DD ) at the second input terminal and producing the programming high voltage (V M ) at the output terminal, the external voltage switch being activated by a fast program enable signal applied to a first one of the enable inputs, the dual mode high voltage power supply operating in a first programming mode in which the programming high voltage is generated from solely the charge pump when the external voltage switch is deactivated and the dual mode high voltage power supply operating in a second programming mode in which the programming voltage is generated from both the charge pump and the external power supply high voltage when the external voltage switch is activated, said output terminal being connected to the output of the charge pump at a common programming node; a plurality of nonvolatile memory blocks, each nonvolatile memory block being connected to a memory block switch having a programming input terminal connected to the common programming node to receive the programming voltage, and each memory block switch having a control input terminal for receiving a signal to activate or deactivate the memory block switch, each of the nonvolatile memory blocks being programmed with the programming voltage when its respective memory block switch is activated; a programming control circuit having an input terminal for receiving the fast program enable signal and a plurality of output terminals being connected to the control input terminals of the memory block switches; an oscillator circuit providing a clock signal; and a divider and hysteresis comparator circuit for providing regulation of the programming voltage, the divider and hysteresis comparator circuit receiving the programming high voltage on a signal input and a reference voltage on a reference input and producing an analog enable signal on an output terminal.
16. The dual mode high voltage power supply of claim 15 further comprising: a flip-flop circuit receiving the clock signal at a clock terminal and the analog enable signal at a data terminal and producing a timing enable signal at an output terminal; and a logic gate receiving the clock signal at a first input terminal and the timing enable signal at a second input terminal and producing the timing signals at an output terminal.
17. The dual mode high voltage power supply of claim 15 wherein the programming high voltage has a value that is regulated by the hysteresis comparator circuit to produce a maximal load line that is the same in both operating modes.
18. The dual mode high voltage power supply of claim 17 wherein the charge pump has an operating clock frequency and an output impedance, said operating clock frequency and output impedance both being constant.
19. The dual mode high voltage power supply of claim 18 wherein the output impedance and the programming voltage are matched by the external power supply high voltage through the means of an internal pass resistor and the external voltage switch.
20. The dual mode high voltage power supply of claim 15 wherein a first number of non-volatile memory blocks are programmed at the same time when the external voltage switch is activated and a second number of non-volatile memory blocks are programmed at the same time the external voltage switch is deactivated, said first number being greater than said second number.
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November 6, 2001
July 22, 2003
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