A method for forming a metal filled semiconductor feature including a low dielectric constant CMP polishing stop layer for improving a CMP polishing process including providing a semiconductor processing surface having a anisotropically etched semiconductor feature formed through a thickness including a second dielectric insulating layer overlying a first dielectric insulating layer, the second dielectric insulating layer having a CMP material removal rate in a CMP process less than about ½ of a CMP material removal rate of the first dielectric insulating layer in the CMP process; filling the anisotropically etched semiconductor feature with a metal to form a metal filled semiconductor feature; and, planarizing according to the CMP process excess material including the metal overlying the second dielectric insulating layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a metal filled semiconductor feature including a low dielectric constant CMP polishing stop layer for improving a CMP polishing process comprising the steps of: providing a semiconductor processing surface having a anisotropically etched semiconductor feature opening formed through a thickness including a fluorinated amorphous carbon second dielectric insulating layer overlying a first dielectric insulating layer, the fluorinated amorphous carbon second dielectric insulating layer having a CMP material removal rate in a CMP process less than about of a CMP material removal rate of the first dielectric insulating layer in the CMP process; filling the anisotropically etched semiconductor feature opening with a metal to include covering the fluorinated amorphous carbon second dielectric insulating layer; and, removing according to the CMP process excess material above the opening level including the metal covering the fluorinated amorphous carbon second dielectric insulating layer.
2. The method of claim 1 , wherein the fluorinated amorphous carbon second dielectric insulating layer has a dielectric constant less than or equal to the first dielectric insulating layer.
3. The method of claim 2 , wherein the first dielectric insulating layer and the fluorinated amorphous carbon second dielectric insulating layer have a dielectric constant of less than about 3.0.
4. The method of claim 1 , wherein the fluorinated amorphous carbon second dielectric insulating layer is formed having a fluorine content of about 40 to about 60 atomic percent.
5. The method of claim 4 , wherein the fluorinated amorphous carbon is formed according to chemical vapor deposition (CVD) process including tri-methyl silane, oxygen, and a fluorine containing gas.
6. The method of claim 4 , wherein the fluorine containing gas includes at least one of CF 4 , CHF 3 , C 2 F 6 , C 3 F 6 , C 3 F 8 , C 4 F 8 , and C 6 F 6 .
7. The method of claim 5 , wherein the CVD process includes one of a plasma enhanced CVD process and a high density plasma CVD process.
8. The method of claim 4 , wherein the fluorinated amorphous carbon second insulating dielectric layer is formed having a thickness of from about 50 Angstroms to about 300 Angstroms.
9. The method of claim 1 , wherein the step of providing includes providing the anisotropically etched semiconductor feature opening formed through the thickness to include a dielectric anti-reflectance coating (DARC) layer comprising one of silicon oxynitride and titanium nitride overlying the second dielectric insulating layer.
10. The method of claim 1 , further including the step of depositing a barrier/adhesion layer including one of a refractory metal and refractory metal nitride prior to the step of filling the anisotropically etched semiconductor feature opening with a metal.
11. The method of claim 10 , further including the step of depositing a seed layer of the metal layer prior to the step of filling the anisotropically etched semiconductor feature opening with a metal.
12. The method of claim 11 , wherein the metal comprises copper or an alloy thereof and the step of filling comprises an electrodeposition process.
13. The method of claim 1 , wherein the fluorinated amorphous carbon second dielectric insulating layer has a CMP material removal rate in the CMP process from about {fraction (1/10)} to about of a CMP material removal rate of the first dielectric insulating layer in the CMP process.
14. The method of claim 1 , wherein the fluorinated amorphous carbon second dielectric insulating layer has a CMP material removal rate in the CMP process of less than 100 Angstroms per minute.
15. A method for forming a copper filled semiconductor feature including a CMP polishing stop layer for improving a CMP polishing process comprising the steps of: providing a semiconductor processing surface having a anisotropically etched semiconductor feature opening formed through a thickness portion including an uppermost anti-reflectance layer overlying a fluorinated amorphous carbon dielectric insulating layer overlying a first dielectric insulating layer, the fluorinated amorphous carbon dielectric insulating layer having a CMP material removal rate in a CMP process less than about of a CMP material removal rate of the first dielectric insulating layer in the CMP process; filling the anisotropically etched semiconductor feature opening according to an electrodeposition process with copper to include covering the uppermost anti-reflectance layer; and, planarizing according to the CMP process including removing material layers overlying the fluorinated amorphous carbon dielectric insulating layer to stop the CMP process on the fluorinated amorphous carbon dielectric insulating layer.
16. The method of claim 15 , wherein the first dielectric insulating layer and the fluorinated amorphous carbon dielectric insulating layer have a dielectric constant of less than about 3.0.
17. The method of claim 15 , wherein the fluorinated amorphous carbon dielectric insulating layer is formed having a fluorine content of about 40 to about 60 atomic percent.
18. The method of claim 17 , wherein the fluorinated amorphous carbon is formed according to chemical vapor deposition (CVD) process including tri-methyl silane, oxygen, and a fluorine containing gas including at least one of CF 4 , CHF 3 , C 2 F 6 , C 3 F 6 , C 3 F 8 , C 4 F 8 , and C 6 F 6 .
19. The method of claim 15 , wherein the fluorinated amorphous carbon dielectric insulating layer is formed having a thickness of from about 50 Angstroms to about 300 Angstroms.
20. The method of claim 15 , wherein the fluorinated amorphous carbon dielectric insulating layer has a CMP material removal rate in the CMP process from about {fraction (1/10)} to about of a CMP material removal rate of the first dielectric insulating layer in the CMP process.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 2, 2002
July 29, 2003
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