A program data latch circuit supplies one of a write bit line potential and a write prohibiting potential corresponding to multilevel data to be written, to a bit line in accordance with a level of a write control signal in a write operation. On the other hand, a program sense latch circuit compares a threshold value of a memory cell transistor sensed through the bit line with a reference potential, changes the level of the write control signal if the threshold value becomes a value corresponding to the multilevel data and instructs output of the write prohibiting potential in a verification operation.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix, wherein said memory cells include storage elements capable of storing multilevel data in a nonvolatile manner, and each of said storage elements has a first node and a second node, and a threshold level of each of said storage elements changed in the nonvolatile manner by applying a voltage at least between said first node and said second node is capable of having one of a plurality of levels corresponding to said multilevel data; a plurality of word lines provided to correspond to rows of said memory cell array, and coupled to said first node of each of said storage elements belonging to the corresponding rows, respectively; a row select circuit capable of selectively supplying a first pulse potential to each of said plurality of word lines in a write operation; a plurality of bit lines provided to correspond to columns of said memory cell array, and coupled to said second node of each of said storage elements belonging to the corresponding columns, respectively; a plurality of program data circuits provided to correspond to said plurality of bit lines, and supplying one of a second potential and a write prohibiting potential corresponding to the multilevel data to be written to said storage elements connected to the corresponding bit lines, to said corresponding bit lines in accordance with a write control signal in the write operation, respectively; and a plurality of program sense circuits provided to correspond to said plurality of bit lines, comparing threshold values of said storage elements sensed through the corresponding bit lines with reference potentials corresponding to said multilevel data to be written in a verification operation, and instructing output of the write prohibiting potential by said write control signal if said threshold values become values corresponding to said multilevel data to be written, respectively.
2. The nonvolatile semiconductor memory device according to claim 1 , further comprising: a potential generation circuit generating a plurality of reference potentials corresponding to said multilevel data, respectively, and a plurality of write bit line potentials corresponding to said multilevel data, respectively; a reference potential select circuit selecting said reference potentials corresponding to said multilevel data to be written from among said plurality of reference potentials, and supplying the selected reference potentials to said plurality of program sense circuits; and a write bit line potential select circuit selecting said second potentials corresponding to said multilevel data to be written from among said plurality of write bit line potentials, and supplying the selected second potentials to said plurality of program data circuits.
3. The nonvolatile semiconductor memory device according to claim 2 , wherein each of said plurality of program data circuits includes a first latch circuit receiving said write prohibiting potential and said second potential, and operating in response to said write prohibiting potential and said second potential, a first held level stored in said first latch circuit is changed in accordance with said write control signal, and said first latch circuit selectively outputs one of said write prohibiting potential and said second potential in accordance with said first held level, and each of said plurality of program sense circuits includes: a second latch circuit having a second held level stored therein and changed in accordance with a comparison result of comparing potential levels of said corresponding bit lines with said reference potentials, and outputting said write control signal in accordance with said second held level; and a potential setting circuit forcedly setting said write control signal to have a level for instructing the output of said second potential in the write operation.
4. The nonvolatile semiconductor memory device according to claim 2 , wherein each of said storage elements is a floating gate transistor having said first node corresponding to a control gate, said second node corresponding to a drain and said threshold value corresponding to a threshold voltage of the floating gate transistor, said nonvolatile semiconductor memory device further comprises a source driving circuit for supplying a predetermined source potential to a source of said floating gate transistor, said row select circuit is capable of selectively supplying a predetermined verification potential to each of said word lines in said verification operation, and said reference potentials correspond to voltages dropped from said predetermined verification potential by said threshold voltages corresponding to said multilevel data to be written.
5. The nonvolatile semiconductor memory device according to claim 4 , wherein said row select circuit is capable of selectively supplying a predetermined read potential to each of said word lines in a read operation, said nonvolatile semiconductor memory device further comprises a plurality of read circuit groups provided to correspond to said plurality of bit lines, respectively, each of said read circuit groups includes a plurality of read circuits receiving a plurality of reference potentials for determining to which levels of the plurality of reference potentials corresponding to said multilevel data, levels of the threshold values of said storage elements correspond, and comparing levels of said plurality of reference potentials with potential levels of said corresponding bit lines, respectively, each of said reference potentials corresponds to a voltage dropped from said predetermined verification potential by one of said threshold voltages corresponding to said multilevel data, and said nonvolatile semiconductor memory device further comprises a data control circuit converting each of the potential levels of said bit lines into one of said multilevel data based on comparison results of said plurality of read circuits.
6. The nonvolatile semiconductor memory device according to claim 5 , wherein each of said plurality of read circuits includes a read latch circuit of which a held level to be stored is changed in accordance with each of said reference potentials and each of the potentials of said bit lines, said nonvolatile semiconductor memory device further comprises a data setting circuit capable of setting the held level of said read latch circuit in accordance with said multilevel data to be written, said reference potential select circuit selects said reference potentials in accordance with the held levels of said plurality of read circuits corresponding to the same bit line, and said bit line potential select circuit selects said second potential in accordance with the held levels of said plurality of read circuits corresponding to the same bit line.
7. The nonvolatile semiconductor memory device according to claim 1 , wherein said memory cell array is an AND type memory cell array.
8. The nonvolatile semiconductor memory device according to claim 1 , wherein said memory cell array is a NAND type memory cell array.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 8, 2002
August 12, 2003
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