Pulse width modulation regulator control circuit having precise frequency and amplitude control

1. A control circuit for a switch mode regulator having a fast discharge cycle, the control circuit having a reference voltage level and a power supply, comprising: an oscillator for providing a periodic carrier signal comprising a sawtooth wave output signal, the oscillator having a first capacitor charged and discharged to the reference voltage to provide the sawtooth wave output signal and a switching circuit coupled to the reference voltage level; and a gain circuit having a reference voltage input, voltage input and an output, the reference voltage input coupled to receive the reference voltage, the voltage input coupled to the first capacitor, the output coupled to the switching circuit to provide feedback proportional to the analog error signal related to the difference between the sawtooth wave output signal and the predetermined reference voltage level.

2. A control circuit as recited in claim 1 , wherein the oscillator comprises: a voltage divider circuit having an input and an output, the input coupled to receive the reference voltage; a first comparator having a positive input, a negative input, and an output, the positive input coupled to receive the reference voltage; a second comparator having a positive input, a negative input, and an output, the positive input coupled to the negative input of the first comparator, the negative input coupled to the output of the voltage divider circuit; a second capacitor coupled between the negative input of the second comparator and ground; a reset flip-flop having a set input, a reset input, an inverting output and a non-inverting output, the set input coupled to the output of the second comparator, the reset input coupled to the output of the first comparator; a first current source coupled to the power supply voltage to provide a charge current during the charge cycle; a first resistor coupled between the first current source and ground; a second current source to provide a charge current during the discharge cycle; a second resistor coupled between the second current source and ground; the first capacitor coupled between ground and the negative input of the first comparator; a first transistor having a gate, a drain and a source, the drain coupled to the first current source, the source coupled to the first capacitor, the gate coupled to the non-inverting output of the reset flip-flop; a second transistor having a gate, a drain and a source, the drain coupled to the first capacitor, the source coupled to the second current source, the gate coupled to the inverting output of the reset flip-flop; and a switching circuit coupled to receive the reference voltage and the output of the gain circuit to modify the sawtooth wave signal.

3. The control circuit as recited in claim 2 , wherein the voltage divider comprises: a third resistor coupled to the reference voltage input; a fourth resistor coupled between the third resistor and ground; and a sixth resistor coupled between the third resistor and the negative input of the second comparator.

4. The control circuit as recited in claim 2 , wherein the switching circuit comprises: a third transistor having a gate, a drain and a source, the source coupled to receive the reference voltage, the gate coupled to the output of the gain circuit; and a third resistor coupled to the drain of the third transistor and the negative input of the second comparator.

5. A control circuit as recited in claim 1 , wherein the gain circuit comprises: a multiphase clock generator for generating a first, second, third and fourth clock signal; a first resistor coupled to the power supply; a first transistor having a source, drain, and gate, the source coupled to the first resistor, the gate coupled to receive the third clock signal; a second transistor having a source, drain, and gate, the drain coupled to the drain of the first transistor, the gate coupled to receive the first clock signal; a second resistor coupled between the reference voltage input and the source of the second transistor; a third resistor coupled to the second resistor; a third transistor having a source, drain, and gate, the source coupled to the source of the second transistor, the gate coupled to receive the third clock signal; a fourth resistor coupled to the voltage input; a fourth transistor having a source, drain, and gate, the source coupled to the fourth resistor, the gate coupled to receive the first clock signal, the drain coupled to the drain of the third transistor; a second capacitor coupled to the drain of the first transistor; a fifth transistor having a source, drain, and gate, the drain coupled to the second capacitor, gate coupled to receive the second clock signal; a fifth resistor coupled between the reference voltage input and the source of the fifth transistor; a sixth resistor coupled to the fifth resistor; a sixth transistor having a source, drain, and gate, the source coupled to the source of the fifth transistor; the gate coupled to receive the second clock signal; a third capacitor coupled between the drain of the third transistor and the drain of the sixth transistor; a fourth capacitor coupled in parallel to the third capacitor; a seventh transistor having a source, drain, and gate, the drain coupled to the drain of the fifth transistor, the gate coupled to receive the fourth clock signal; a eight transistor having a source, drain, and gate, the drain coupled to the drain of the sixth transistor, gate coupled to receive the fourth clock signal, the source coupled to the source of the seventh transistor; a fifth capacitor coupled between the source of the eighth transistor and the output; a ninth transistor having a source, drain, and gate, the drain coupled to the source of the seventh transistor, gate coupled to receive the power up/clear signal, source coupled to the output; and a comparator, having a positive input, a negative input and an output, the negative input coupled to the source of the eighth transistor, the positive input coupled to the reference voltage input, the output coupled to the output of the gain circuit.

6. A control circuit for a switch mode power converter having a reference voltage, a power supply voltage and ground, comprising: a voltage divider circuit having an input and an output, the input coupled to receive the reference voltage; a first comparator having a positive input, a negative input, and an output, the positive input coupled to receive the reference voltage; a second comparator having a positive input, a negative input, and an output, the positive input coupled to the negative input of the first comparator, the negative input coupled to the output of the voltage divider circuit; a first capacitor coupled between the negative input of the second comparator and ground; a reset flip-flop having a set input, a reset input, an inverting output and a non-inverting output, the set input coupled to the output of the second comparator, the reset input coupled to the output of the first comparator; a first current source coupled to the power supply voltage to provide a charge current during the charge cycle; a first resistor coupled between the first current source and ground; a second current source to provide a charge current during the discharge cycle; a second resistor coupled between the second current source and ground; a second capacitor coupled between ground and the negative input of the first comparator; a first transistor having a gate, a drain and a source, the drain coupled to the first current source, the source coupled to the second capacitor, the drain coupled to the non-inverting output of the reset flip-flop; a second transistor having a gate, a drain and a source, the drain coupled to the second capacitor, the source coupled to the second current source, the gate coupled to the inverting output of the reset flip-flop; a third transistor having a gate, a drain and a source, the source coupled to receive the reference voltage, the gate coupled to the output of the gain circuit; a third resistor coupled to the drain of the third transistor and the negative input of the second comparator; and a gain circuit having a first and second input and an output, the first coupled to receive the reference voltage, the second input coupled to the second capacitor, the output coupled to the gate of the third transistor to provide feed back proportional to the voltage error.

7. A control circuit for a switch mode regulator, having a fast charge cycle, the control circuit having a reference voltage level and a power supply, comprising: an oscillator for providing a periodic carrier signal comprising a sawtooth wave output signal, the oscillator having a first capacitor charged and discharged to the power supply voltage to provide the sawtooth wave output signal and a switching circuit coupled to the reference voltage level; and a gain circuit having a reference voltage input, voltage input and an output, the reference voltage input coupled to receive the reference voltage, the voltage input coupled to the first capacitor, the output coupled to the switching circuit to provide feedback proportional to the analog error signal related to the difference between the sawtooth wave output signal and the predetermined reference voltage level.

8. A control circuit as recited in claim 7 , wherein the oscillator comprises: a voltage divider circuit having an input and an output, the input coupled to receive the reference voltage; a first comparator having a positive input, a negative input, and an output, the positive input coupled to receive the reference voltage; a second comparator having a positive input, a negative input, and an output, the positive input coupled to the negative input of the first comparator, the negative input coupled to the output of the voltage divider circuit; a second capacitor coupled between the negative input of the second comparator and ground; a reset flip-flop having a set input, a reset input, an inverting output and a non-inverting output, the set input coupled to the output of the second comparator, the reset input coupled to the output of the first comparator; a first current source coupled to the power supply voltage to provide a charge current during the charge cycle; a first resistor coupled between the first current source and ground; a second current source to provide a charge current during the discharge cycle; a second resistor coupled between the second current source and ground; the first capacitor coupled between ground and the negative input of the first comparator; a first transistor having a gate, a drain and a source, the drain coupled to the first current source, the source coupled to the first capacitor, the gate coupled to the non-inverting output of the reset flip-flop; a second transistor having a gate, a drain and a source, the drain coupled to the first capacitor, the source coupled to the second current source, the gate coupled to the inverting output of the reset flip-flop; and a switching circuit coupled to receive the reference voltage and the output of the gain circuit to modify the sawtooth wave signal.

9. The control circuit as recited in claim 8 , wherein the voltage divider comprises: a third resistor coupled to the reference voltage input; and a fourth resistor coupled between the third resistor to form a node, the node coupled to the negative input of the second comparator.

10. The control circuit as recited in claim 8 , wherein the switching circuit comprises: a third transistor having a gate, a drain and a source, the source coupled to receive the reference voltage, the gate coupled to the output of the gain circuit; and a third resistor coupled to the drain of the third transistor and the negative input of the second comparator.

11. A control circuit as recited in claim 7 , wherein the gain circuit comprises: a multiphase clock generator for generating a first, second, third and fourth clock signal; a first resistor coupled to the power supply; a first transistor having a source, drain, and gate, the source coupled to the first resistor, the gate coupled to receive the third clock signal; a second transistor having a source, drain, and gate, the drain coupled to the drain of the first transistor, the gate coupled to receive the first clock signal, the source coupled to the reference voltage input; a third transistor having a source, drain, and gate, the source coupled to the source of the second transistor, the gate coupled to receive the third clock signal; a second resistor coupled to the voltage input; a fourth transistor having a source, drain, and gate, the source coupled to the fourth resistor, the gate coupled to receive the first clock signal, the drain coupled to the drain of the third transistor; a second capacitor coupled to the drain of the first transistor; a fifth transistor having a source, drain, and gate, the drain coupled to the second capacitor, gate coupled to receive the second clock signal, the source coupled to the reference voltage input; a sixth transistor having a source, drain, and gate, the source coupled to the source of the fifth transistor; the gate coupled to receive the second clock signal; a third capacitor coupled between the drain of the third transistor and the drain of the sixth transistor; a seventh transistor having a source, drain, and gate, the drain coupled to the drain of the fifth transistor, the gate coupled to receive the fourth clock signal; a eight transistor having a source, drain, and gate, the drain coupled to the drain of the sixth transistor, gate coupled to receive the fourth clock signal, the source coupled to the source of the seventh transistor; a fourth capacitor coupled between the source of the eighth transistor and the output; a ninth transistor having a source, drain, and gate, the drain coupled to the source of the seventh transistor, gate coupled to receive the power up/clear signal, source coupled to the output; and a comparator, having a positive input, a negative input and an output, the negative input coupled to the source of the eighth transistor, the positive input coupled to the reference voltage input, the output coupled to the output of the gain circuit.

12. A control circuit for a switch mode power converter having a reference voltage, a power supply voltage and ground, comprising: a voltage divider circuit having an input and an output, the input coupled to receive the reference voltage; a first comparator having a positive input, a negative input, and an output, the positive input coupled to receive the reference voltage; a second comparator having a positive input, a negative input, and an output, the positive input coupled to the negative input of the first comparator, the negative input coupled to the output of the voltage divider circuit; a first capacitor coupled between the negative input of the second comparator and ground; a reset flip-flop having a set input, a reset input, an inverting output and a non-inverting output, the set input coupled to the output of the second comparator, the reset input coupled to the output of the first comparator; a first current source coupled to the power supply voltage to provide a charge current during the charge cycle; a first resistor coupled between the first current source and ground; a second current source to provide a charge current during the discharge cycle; a second resistor coupled between the second current source and ground; a second capacitor coupled between ground and the negative input of the first comparator; a first transistor having a gate, a drain and a source, the drain coupled to the first current source, the source coupled to the second capacitor, the drain coupled to the non-inverting output of the reset flip-flop; a second transistor having a gate, a drain and a source, the drain coupled to the second capacitor, the source coupled to the second current source, the gate coupled to the inverting output of the reset flip-flop; a third transistor having a gate, a drain and a source, the source coupled to receive the reference voltage, the gate coupled to the output of the gain circuit; a third resistor coupled to the drain of the third transistor and the negative input of the second comparator; and a gain circuit having a first and second input and an output, the first coupled to receive the reference voltage, the second input coupled to the second capacitor, the output coupled to the gate of the third transistor to provide feed back proportional to the voltage error.