A micromachined electromechanical random access memory (MEMRAM) array is disclosed which includes a plurality of MEM memory cells, where each MEM memory cell has an MEM switch and a capacitor. The MEM switch includes a contact portion configured for moving from a first position to a second position for reading out a charge stored within the capacitor or for writing the charge to the capacitor. A method is also disclosed for fabricating each MEM memory cell of the MEMRAM array.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory system comprising a plurality of micromachined electromechanical memory ( MEM ) cells arranged in an array, each of said MEM cells comprising a MEM switch and a capacitor, said MEM switch comprising a switching element and a fixed end for supporting said switching element, said switching element comprising a cantilever beam, said fixed end comprising at least one fixed end support portion and a contact portion, wherein each of the plurality of MEM cells is configured for storing a charge therein.
2. The memory system according to claim 1 , wherein the switch includes a contact portion configured for moving from a first position to a second position for reading out the charge stored within the capacitor or for writing the charge to the capacitor.
3. The memory system according to claim 2 , wherein the contact portion shorts a bitline to a plate of the capacitor when said contact portion is in the second position.
4. The memory system according to claim 2 , wherein the switch includes a fixed end opposite the contact portion.
5. The memory system according to claim 1 , wherein a plurality of datalines traverse the array.
6. The memory system according to claim 5 , wherein the plurality of datalines include bitlines and wordlines.
7. The memory system according to claim 6 , wherein the bitlines and wordlines are embedded within the plurality of MEM memory cells.
8. The memory system according to claim 1 , wherein each of the plurality of MEM memory cells is connected to at least one respective MOS device.
9. The memory system according to claim 1 , wherein the plurality of MEM memory cells are fabricated on a semiconductor SOI or bulk substrate.
10. The memory system according to claim 1 , wherein each of the plurality of MEM memory cells has a planar cell structure.
11. A memory system as in claim 1 , wherein a read operation to said MEM cell comprises the following: activation of a wordline causing a corresponding bitline to short said capacitor, said short causing an electrical potential to build up between said wordline and said MEM switch, said electrical potential reaching a threshold causing said MEM switch to bridge said bitline to said capacitor.
12. A micromachined electromechanical random access memory (MEMRAM) array comprising: a plurality of micromachined electromechanical memory ( MEM ) cells, each of said MEM cells comprising a MEM switch and a capacitor, said MEM switch comprising a switching element and a fixed end for supporting said switching element, said switching element comprising a cantilever beam, said fixed end comprising at least one fixed end support portion and a contact portion, wherein each of the plurality of MEM cells is configured for storing a charge therein.
13. The array according to claim 12 , wherein the switch includes a contact portion configured for moving from a first position to a second position for reading out the charge stored within the capacitor or for writing the charge to the capacitor.
14. The array according to claim 13 , wherein the contact portion shorts a bitline to a plate of the capacitor when said contact portion is in the second position.
15. The array according to claim 12 , wherein the switch includes a fixed end opposite the contact portion.
16. The array according to claim 12 , wherein a plurality of datalines traverse the array.
17. The array according to claim 16 , wherein the plurality of datalines include bitlines and wordlines.
18. The array according to claim 17 , wherein the bitlines and wordlines are embedded within the plurality of MEM memory cells.
19. The array according to claim 12 , wherein each of the plurality of MEM memory cells is connected to at least one respective MOS device.
20. The array according to claim 12 , wherein the plurality of MEM memory cells are fabricated on a semiconductor SOI or bulk substrate.
21. The array according to claim 12 , wherein each of the plurality of MEM memory cells has a planar cell structure.
22. A memory system as in claim 12 , wherein a read operation to said MIEM cell comprises the following: activation of a wordline causing a corresponding bitline to short said capacitor, said short causing an electrical potential to build up between said wordline and said MEM switch, said electrical potential reaching a threshold causing said MEM switch to bridge said bitline to said capacitor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 12, 2001
August 26, 2003
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.