To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, address for salvaging defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit, thereby, a special process is not needed in forming the nonvolatile memory element, that is, the nonvolatile memory element can be formed in a process of forming CMOS device and apparatus of laser beam for programming is not needed since the programming is carried out in testing, time necessary for programming can be shortened and therefore, testing cost can be reduced.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor integrated circuit device comprising: a volatile memory cell array including volatile memory cells; volatile redundant memory cells to substitute for a deficient memory cell when there is such a deficient memory cell which is a volatile memory cell having a defect in the volatile memory cell array; a nonvolatile memory to store redundant address information based on the deficient memory cell; and a redundant decoder coupled to the nonvolatile memory to replace an output from the deficient memory cell with an output from the redundant memory cells based on the redundant address information stored in the nonvolatile memory, wherein the nonvolatile memory includes a first semiconductor area of a first conductivity type formed in a main surface of a semiconductor substrate, a second semiconductor area of a second conductivity type provided adjacent to the first semiconductor area in said main surface of said semiconductor substrate and a floating gate arranged to interpose an insulating film of the nonvolatile memory between the first and the second semiconductor areas and the floating gate, and wherein a source area of the second conductivity type and a drain area of the second conductivity type are provided in the first semiconductor area; wherein data can be erased or written by applying a predetermined voltage to the second semiconductor area and to at least one of the source area and the drain area.
2. A semiconductor integrated circuit device as claimed in claim 1 , further comprising: a pad connected to a lead frame to input or output signals; and an input/output circuit, coupled to the volatile memory array and the volatile redundant memory cells, including a second transistor and connected to the pad to input or output the signals; wherein the volatile memory cell array includes a first transistor, and wherein an insulating film of the second transistor is thicker than an insulating film of the first transistor.
3. The semiconductor integrated circuit device according to claim 2 : wherein the insulating film of the nonvolatile memory is provided with a film thickness thicker than a film thickness of the insulating film of the first transistor and is provided with a film thickness substantially equal to a film thickness of the insulating film of the second transistor.
4. The semiconductor integrated circuit device according to claim 2 : wherein a difference between a film thickness of the insulating film of the nonvolatile memory and a film thickness of the insulating film of the first transistor is larger than a difference between the film thickness of the insulating film of the nonvolatile memory and the film thickness of the insulating film of the second transistor.
5. The semiconductor integrated circuit device according to claim 2 : wherein a gate length of the first transistor is shorter than a gate length of the nonvolatile memory.
6. The semiconductor integrated circuit device according to claim 2 : wherein the nonvolatile memory is arranged at an area arranged with the pad and the input/output circuit.
7. The semiconductor integrated circuit device according to claim 2 : wherein a plurality of the pads are provided to the semiconductor integrated circuit device and at least one of the plurality of the pads is capable of selectively inputting the signals and control signals to control writing data to the nonvolatile memory.
8. A semiconductor integrated circuit device comprising: a volatile memory cell array including volatile memory cells; volatile redundant memory cells to substitute for a deficient memory cell when there is such a deficient memory cell which is a volatile memory cell having a defect in the volatile memory cell array; a nonvolatile memory to store redundant address information based on the deficient memory cell; an error correcting circuit; and a redundant decoder to control to replace an output from the deficient memory cell with an output from redundant memory cells based on the redundant address information stored in the nonvolatile memory, wherein the nonvolatile memory includes a first element formed in a first semiconductor area of a first conductivity type formed in a main surface of a semiconductor substrate and a second element forfried in a second semiconductor area of a second conductivity type formed in said main surface of said semiconductor substrate, the first element includes a source area and a drain area formed in the first semiconductor area and a first gate formed via a first insulating film and the second element includes a second gate formed via a second insulating film and connected to the first gate; and wherein the error correcting circuit is coupled to the nonvolatile memory and the redundant decoder and attaches a check bit to the redundant address information to thereby store the redundant address information with the check bit in the nonvolatile memory and executes an error correcting processing to data read from the nonvolatile memory to output to the redundant decoder.
9. The semiconductor integrated circuit device according to claim 8 : wherein the error correcting circuit is capable of correcting up to 1 bit of error with respect to the redundant address information.
10. The semiconductor integrated circuit device comprising: nonvolatile memories to store redundant address information or trimming information; a decoder to decode the redundant address information or the trimming information stored in the nonvolatile memory cells; and a switch circuit controlled by the decoder; wherein each of the nonvolatile memories includes a first and a second nonvolatile memory cells each having a first semiconductor area of a first conductivity type formed in a main surface of a semiconductor substrate, a second semiconductor area of a second conductivity type formed in said main surface of said semiconductor substrate, a source area and a drain area of the second conductivity type formed in the first semiconductor area and gate electrodes formed by respectively interposing insulating films between the first semiconductor area and the second semiconductor area and the gate electrodes; and wherein 1 bit information is stored by the first and the second nonvolatile memory cells.
11. The semiconductor integrated circuit device according to claim 10 : wherein the first and the second nonvolatile memory cells store the same information and read the 1 bit information by outputting a logical sum of data respectively outputted from the nonvolatile memory cells.
12. The semiconductor integrated circuit device according to claim 10 : wherein the first nonvolatile memory cell stores a first signal and the second nonvolatile memory cell stores a second signal under a complimentary relationship with the first signal, and wherein the 1 bit information is read by detecting a difference between a threshold voltage of the first nonvolatile memory cell and a threshold voltage of the second nonvolatile memory cell.
13. The semiconductor integrated circuit device according to claim 12 : wherein a gate width of the first nonvolatile memory cell and a gate width of the second nonvolatile memory cell differ from each other and predetermined data can be outputted before writing information to the nonvolatile memories.
14. A semiconductor integrated circuit device according to claim 8 wherein the first and second semiconductor areas are formed adjacent to one another in said main surface of said semiconductor substrate.
15. A semiconductor integrated circuit device according to claim 10 wherein the first and second semiconductor areas are formed adjacent to one another in said main surface of said semiconductor substrate.
16. A semiconductor integrated circuit device comprising: a volatile memory cell array including volatile memory cells; volatile redundant memory cells to substitute for defective volatile memory cells in said volatile memory cell array; a nonvolatile memory to store redundant address information based on defective volatile memory cells in said volatile memory cell array; a redundant decoder, coupled to said nonvolatile memory and outputs of said volatile memory cell array and the volatile redundant memory cells, to replace an output from a defective volatile memory cell in said volatile memory cell array with an output of one of said redundant memory cells, wherein said nonvolatile memory is comprised of nonvolatile floating gate transistors each having a floating gate and a control gate arranged in a side by side arrangement to one another over a main surface of a semiconductor substrate in which said nonvolatile memory is formed.
17. A semiconductor integrated circuit device according to claim 16 , wherein said floating gate and said control gate are fabricated by a same layer of polycrystalline silicon.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 12, 2001
August 26, 2003
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