Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a semiconductor device with a reduced gate resistance and a self-aligned contact pad, the method comprising: forming a first dummy gate pattern and a second dummy gate pattern on a semiconductor substrate, each dummy gate pattern having a sidewall spacer, the second dummy gate pattern relatively being wider than the first dummy gate pattern; forming a first insulating layer on an entire surface of the semiconductor substrate, the first insulating layer having a planar top surface and having the same level in height as the dummy gate patterns; removing the first and second dummy gate patterns to form a first and a second grooves exposing the substrate; forming a first and a second gate oxide layers on the first and the second grooves respectively; forming a low resistance material layer on the first insulating layer thereby completely filling the first groove and partially filling the second groove due to width difference therebetween; forming an etching stopper on the conductive material to completely fill the remainder second groove; etching the etching stopper until the conductive material outside of the grooves is exposed; using remainder etching stopper as an etch mask and etching the conductive material layer in the first groove to recess from a top surface of the first insulating layer; and forming an insulator to fill remainder first and second grooves to form a first capping layer and a second capping layer.
2. The method according to claim 1 , wherein the act of removing the first and second dummy gate patterns to form a first and a second grooves exposing the substrate is followed by the acts of: removing the sidewall spacer and a portion of the first insulating layer on a top edge of the groove to enlarge the width of the grooves, the enlarged grooves having substantial vertical sidewall profile; and forming reverse sidewall spacers on a sidewall of the enlarged grooves, thereby narrowing a bottom of the resulting groove as compared to a top thereof.
3. The method according to claim 2 , wherein the sidewall spacer is formed of the same material as the first insulating layer and the reverse sidewall spacer is formed of a material that has an etching selectivity with respect to the first insulating layer.
4. The method according to claim 1 , wherein the etching stopper is formed of photoresist layer or spin-on-glass layer.
5. The method according to claim 1 , wherein the capping layer and the sidewall spacer are formed of silicon nitride respectively and the first and the second insulating layer are formed of silicon oxide respectively.
6. The method according to claim 5 , further comprising the acts of: forming a second insulating layer on the first insulating layer and the capping layer, the second insulating layer having an etching selectivity with respect to the sidewall spacer and the capping layer; and selectively etching the second and first insulating layers with respect to the spacer and capping layer to form a self-aligned contact opening exposing the substrate outside of the gate electrode.
7. The method according to claim 1 , further comprising removing the remainder etching stopper layer from the second groove.
8. A method of forming an integrated circuit device, the method comprising: forming a first and second spaced apart dummy gates on a substrate, the first and second dummy gates having respective first and second side wall spacers thereon, the second dummy gate being wider than the first dummy gate; removing the first and second dummy gates to form first and a second grooves; and forming a gate electrode in the first groove to a first level and in the second groove to a second level that is less than the first level due to the second groove being wider than the first groove.
9. A method according to claim 8 wherein the act of removing comprises: dry etching the first and second dummy gates; and then wet etching the first and second dummy gates.
10. A method of forming an integrated circuit device, the method comprising: forming first and second spaced apart dummy gates on a substrate, the first and second dummy gates having respective first and second side wall spacers thereon, the second dummy gate being wider than the first dummy gate; removing the first and second dummy gates to form first and second grooves in the substrate; and forming a conductive material in the first groove to a first level and in the second groove to a second level that is less than the first level.
11. A method according to claim 10 wherein the step of forming the conductive material comprises: forming an insulating layer on the substrate and in the first and second grooves; forming the conductive material in the first and second grooves recessed from an opening of the first and second grooves; removing an amount of the conductive material to leave conductive material in the first and second grooves.
12. A method according to claim 11 wherein the step of forming the conductive material comprises: etching the conductive material to recess the conductive material into the first and second grooves.
13. A method according to claim 11 wherein the insulating layer comprises a first insulating layer, the method further comprising: forming a second insulating layer on the first insulating layer; etching a contact hole through the first and second insulating layers to expose an active region of the substrate; and forming a contact in the contact hole self-aligned to the active region.
14. A method according to claim 11 wherein an opening of the first groove is wider than a base of the first groove.
15. A method according to claim 11 wherein the conductive material is selected from a group consisting of TiN/W, polysilicon and polysilicon/silicide.
16. A method according to claim 11 wherein the insulating layer is selected from a group consisting of silicon oxide, silicon oxynitride, and tantalum oxide, the sidewall spacer and the capping layer are formed of silicon nitride layer, respectively.
17. A method according to claim 11 wherein the step of forming a conductive material in the groove comprises: forming the conductive material in the first and second grooves on the insulating layer to completely fill the first and second grooves; planarizing the conductive material until a top surface of the insulating layer is exposed; and selectively etching back the conductive material into the first groove to a selected depth from a top surface of the insulating layer.
18. A method according to claim 10 wherein the step of forming a conductive material in the first and second grooves comprises: forming the conductive material conformally in the first and second grooves; forming an etching stopper on the conformal conductive material; etching the etching stopper and the conductive material outside of the first and second grooves; and removing a remaining portion of the etching stopper from the first and second grooves.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 9, 2001
September 2, 2003
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