A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact region 353 at a surface of a semiconductor substrate 300. The transistor, with the exception of the contact region, is covered with a first material 362, 366 and the first material and the contact region are then covered with a layer of a second material 370. The portion of the second layer covering the contact region is removed to expose the contact region so that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layer 372 in the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layer 376 over the first conductive layer, and forming a second conductive layer 378 over the dielectric layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for fabricating an integrated circuit, comprising the steps of: forming a contact region in a semiconductor material structure; covering said semiconductor material structure, excluding said contact region, with a first material; covering said first material and said contact region with a layer of a second material; removing portions of said layer of second material and exposing said contact region, said removal of said portions of said layer of second material and exposing said contact region forming a cavity characterized by a bottom of an upper portion being said first material and sides of said upper portion being second material; and forming a conductive layer in said cavity to contact said contact region and conform to said bottom and sides.
2. The method of claim 1 , further comprising the steps of: forming a dielectric layer over said conductive layer; and forming a second conductive layer over said dielectric layer.
3. The method of claim 1 , wherein said step of covering said semiconductor material structure with a first material comprises depositing a nitride layer over a bitline and nitride sidewalls on said bitline.
4. The method of claim 1 , wherein said step of covering said first material and said contact region comprises depositing an oxide layer.
5. The method of claim 1 , wherein said step of forming a conductive layer in said cavity comprises depositing doped polysilicon.
6. The method of claim 2 , wherein said step of forming a dielectric layer comprises forming a layer of nitride following by oxidation of said nitride.
7. The method of claim 2 , wherein said step of forming a second conductive layer comprises depositing doped polysilicon.
8. A method for fabricating a memory integrated circuit, comprising the steps of: forming a transistor comprising wordline and first and second contact regions at a first surface of a substrate; forming a bitline in contact with said first contact region; forming a first layer of a first material over said bitline; forming a second layer of a second material over said first layer; exposing said second contact region by forming a cavity through said second layer, said cavity with an upper portion having a substantially horizontal bottom surface at said first layer and substantially vertical sides at said second layer; and forming a conductive layer in said cavity to contact said second contact region and conform to said bottom and sides.
9. The method of claim 8 , further comprising the steps of: forming a dielectric layer over said conductive layer; forming a second conductive layer over said dielectric layer.
10. The method of claim 8 , further comprising the step of forming sidewalls on said bitline.
11. The method of claim 10 , wherein said step of forming sidewalls comprises forming nitride sidewalls.
12. The method of claim 8 , wherein said step of forming a first layer of a first material over said bitline comprises depositing nitride.
13. The method of claim 8 , wherein said step of forming a second layer of a second material over said first layer comprising depositing oxide.
14. The method of claim 8 , wherein said step of forming a first conductive layer in said cavity comprises depositing doped polysilicon.
15. The method of claim 9 , wherein said step of forming a dielectric layer comprises forming a layer of nitride following by oxidation of said nitride.
16. The method of claim 9 , wherein said step of forming a second conductive layer comprises depositing doped polysilicon.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 14, 1997
September 9, 2003
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