A silicon on insulator substrate is provided to include the following: a handle wafer; a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region extending from the layer of bonding material upward into the device wafer; and an epitaxial silicon layer provided on a second surface of the device wafer. The silicon on insulator substrate with this configuration can be made with a minimal possible thickness.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A silicon on insulator substrate, comprising: a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region extending from said layer of bonding material upward into said device wafer; and an epitaxial silicon layer provided on a second surface of the device wafer.
2. The substrate of claim 1 wherein the thickness of the device wafer is defined by the minimum possible thickness utilized by the process to form said device wafer.
3. The substrate of claim 1 wherein the thickness of the device wafer is in a range of about 1-3 microns.
4. The substrate of claim 1 wherein a portion of said implant region is provided in said epitaxial layer.
5. The substrate of claim 1 wherein a measure of the capacitance of said substrate is greater than or equal at said oxide and said surface.
6. The substrate of claim 1 wherein the buried region has a doping concentration gradient which is greater at a point adjacent to the bonding oxide than at a point farther away from the bonding oxide.
7. The substrate of claim 1 wherein the buried region extends into the epitaxial layer.
8. The substrate of claim 1 wherein the device layer has a thickness and the buried region has a depth in said device region of at least one half the thickness of the device layer.
9. A semiconductor device comprising: a handle wafer; a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region extending from said layer of bonding material upward into said device wafer; an epitaxial silicon layer provided on a second surface of the device wafer; at least one active region provided in the device wafer and epitaxial silicon layer; and a buried region provided in the device wafer having a greater concentration of dopant atoms at a point in the device wafer closer to the bonding material than at a second point farther from the bonding material.
10. The semiconductor device of claim 9 wherein the device active region includes: a base region; a collector region; and an emitter region.
11. The semiconductor device of claim 10 wherein the active region further includes a surface, and the device further includes a first metal interconnect formed on the surface coupled to said collector, a second metal interconnect coupled to said emitter, and a third metal interconnect coupled to said base region.
12. The semiconductor device of claim 9 further including a sinker region intersecting said buried region.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 6, 2002
September 9, 2003
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