A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled through a clock tree, and a feedback signal is generated that is indicative of the propagation delay of the internal clock signal through the clock tree. The feedback signal is applied to the synchronized mirror delay to allow the synchronized mirror delay to delay the internal clock signal by a delay interval that compensates for the propagation delay in the clock tree. A lock detector may be used to initially generate the internal clock signal directly from the external clock signal. A fine delay circuit that delays the internal clock signal in relatively fine increments may be used to couple the internal clock signal to the clock tree.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A clock skew compensation circuit, comprising: a synchronized mirror delay having an output terminal, a measurement delay line input terminal, and a variable delay line input terminal; an input buffer having an input terminal coupled to receive an external clock signal and an output terminal coupled to the variable delay line input terminal of the synchronized mirror delay; and a clock tree coupled to the output terminal of the synchronized mirror delay, the clock tree having a feedback node, the feedback node being coupled to the measurement delay line input terminal to provide a delayed feedback signal corresponding to a signal coupled from the feedback node of the clock tree.
2. The clock skew compensation circuit of claim 1 wherein the input buffer delays the external clock signal by a first delay value; and wherein the clock skew compensation circuit further comprises a model delay circuit coupled between the feedback node of the clock tree and the measurement delay line input terminal, the model delay circuit providing a delay substantially equal to the first delay value so that the delayed feedback signal applied to the measurement delay line input terminal corresponds to the signal from the feedback node of the clock tree delayed by substantially the first delay value.
3. The clock skew compensation circuit of claim 2 further comprising: a clock driver coupling the output of the synchronized mirror delay to the clock tree, the clock driver providing a delay of a second delay value, and wherein the model delay circuit further provides a delay substantially equal to the second delay value so that the delayed feedback signal applied to the measurement delay line input terminal corresponds to the signal from the feedback node of the clock tree delayed by substantially the sum of the first delay value and the second delay value.
4. The clock skew compensation circuit of claim 1 further comprising: a switch having a first input terminal coupled to receive the external clock signal, a second input terminal coupled to the output terminal of the synchronized mirror delay, an output terminal coupled to the clock tree and a control terminal for coupling the output terminal to the first input terminal responsive to a control signal applied to the control terminal having a first state and coupling the output terminal to the second input terminal responsive to the control signal having a second state; and a detector coupled to the control input of the switch and being operable to determine when the synchronized mirror delay has stabilized, the detector being operable to generate the control signal having the first state prior to determining the synchronized mirror delay has stabilized and to generate the control signal having the second state responsive to determining the synchronized mirror delay has stabilized.
5. The clock skew compensation circuit of claim 4 wherein the detector comprises a logic circuit that is operable to generate the control signal having the first state prior to the lapse of a predetermined number of periods of the external clock signal, and is operable to generate the control signal having the second state responsive to the lapse of the predetermined number of periods of the external clock signal.
6. The clock skew compensation circuit of claim 5 wherein the predetermined number of periods of the external clock signal is two periods of the external clock signal.
7. The clock skew compensation circuit of claim 1 further comprising: a fine delay line coupled between the output of the synchronized mirror delay and the clock tree, the fine delay line varying the delay of the fine delay line responsive to a delay control signal applied to a control terminal of the fine delay line; a phase detector having a first input terminal to an output terminal of the fine delay line, a second input terminal, and an output terminal coupled to the control terminal of the fine delay line, the phase detector generating the delay control signal as a function of the phase difference between signal applied to its first and second input terminals; and a delay model circuit operable to provide a predetermined delay, the delay model circuit coupling the delayed feedback signal from the clock tree to the second input terminal of the phase detector.
8. The clock skew compensation circuit of claim 7 wherein the delay model circuit comprises a delay circuit having a delay with a delay magnitude that is substantially less than the delay of the synchronized mirror delay.
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August 29, 2001
September 9, 2003
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