Non-volatile, electrically alterable semiconductor memory, including at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns, column selection circuitry for selecting columns among the plurality of columns, and a write circuit for simultaneously writing a first number of memory cells. A plurality of doped semiconductor regions is provided, extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block that can be individually erased. The plurality of doped semiconductor regions define a plurality of column packets each one containing a second number of columns equal to or higher than the first number, memory cells belonging to columns of a same column packet being formed in a same doped semiconductor region distinct from the doped semiconductor regions in which memory cells belonging to columns of the other column packets are formed. The column selection circuits are such that within each column packet columns containing memory cells that can be written simultaneously by the write circuit are distributed among the columns of the column packet so as to be at the substantially maximum distance from each other allowable within the column packet.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A non-volatile, electrically alterable semiconductor memory comprising: at least one array of memory cells arranged in a plurality of rows and a plurality of columns; a write circuit for simultaneously writing a selected number of memory cells; a plurality of doped semiconductor regions extending transversely to the rows and dividing the memory cells of each row into a plurality of subsets of memory cells, each subset of memory cells within the same doped semiconductor region defining an independently erasable memory block; a plurality of column packets, each column packet comprising at least one column of memory cells, the number of columns of memory cells in each column packet being greater than or equal to the selected number of memory cells; and a column selection circuit for selecting columns of memory cells such that columns of memory cells comprising memory cells that are simultaneously written by said write circuit are distributed among said plurality of column packets so as to be a maximum distance from one another within each column packet.
2. A non-volatile, electrically alterable semiconductor memory according to claim 1 further comprising a doped semiconductor region selection circuit comprising a doped semiconductor region address signal line bus and a doped semiconductor region address decoding and selection circuit for selectively supplying to said plurality of doped semiconductor regions respective biasing voltages based on an operation mode of the memory.
3. A non-volatile, electrically alterable semiconductor memory according to claim 2 further comprising a row selection circuit for selecting at least one row of memory cells from among said plurality of rows during an erase operation to supply a row erase voltage to only the selected at least one row of memory cells.
4. A non-volatile, electrically alterable semiconductor memory according to claim 1 wherein said column selection circuit comprises: a column address signal line bus for carrying a digital code defining a column address; and column address decoding and column selection circuits for receiving the column address defined by the digital code and, based thereon, selecting a column packet from among said plurality of column packets and selecting a number of columns of memory cells within the selected column packet; the number of columns of memory cells selected being equal to the selected number of memory cells and the columns of memory cells being distributed among the columns of memory cells of the column packet so as to be a maximum distance from one another within the column packet.
5. A non-volatile, electrically alterable semiconductor memory according to claim 1 wherein said column selection circuit comprises: a column address signal line bus for carrying an externally-generated digital code defining a column address; a digital code transformation circuit to generate an internal digital code based on the externally-generated digital code; and column address decoding and column selection circuits for receiving the internal digital code and, based thereon, selecting a column packet and a number of columns of memory cells within the column packet, the number of columns of memory cells selected being equal to the selected number of memory cells; the generation of the internal digital code such that the columns of memory cells selected are a maximum distance from one another within the column packet.
6. A non-volatile, electrically alterable semiconductor memory according to claim 1 wherein the selected number of said memory cells is equal to 2 n ; wherein the number of columns of memory cells in each column packet is equal to 2 m ; wherein said column selection circuit is such that, within each column packet, columns of memory cells containing memory cells written simultaneously by said write circuit are distributed every 2 (m n) columns of the column packet.
7. A memory comprising: at least one array of memory cells arranged in a plurality of columns and a plurality of rows; a write circuit to write a selected number of said memory cells; a plurality of doped semiconductor regions dividing said at least one array of memory cells into a plurality of subsets of memory cells, each subset of memory cells within a doped semiconductor region comprising an independently erasable memory block; a plurality of column packets, each column packet comprising at least one column of memory cells, the number of columns of memory cells in each column packet being greater than or equal to the selected number of memory cells; a row selection circuit for selecting at least one row of memory cells from among said plurality of rows during an erase operation to supply a row erase voltage to the selected at least one row of memory cells; a column selection circuit for selecting columns of memory cells such that columns of memory cells comprising memory cells written by said write circuit are distributed among said plurality of column packets so as to be a maximum distance from one another within each column packet.
8. A memory according to claim 7 further comprising a doped semiconductor region address signal line bus and a doped semiconductor region address decoding and selection circuit to selectively supply to said plurality of doped semiconductor regions respective biasing voltages based on an operation mode.
9. A memory according to claim 7 wherein said column selection circuit comprises: a column address signal line bus for carrying a digital code defining a column address; and column address decoding and column selection circuits for receiving the column address and, based thereon, performing a selection of a column packet from among said plurality of column packets and a selection of a number of columns of memory cells within the selected column packet; the number of selected columns of memory cells being equal to said selected number of memory cells and the selected columns of memory cells being distributed among the columns of memory cells of the selected column packet so as to be a maximum distance from one another within the column packet.
10. A memory according to claim 7 wherein said column selection circuit comprises: a column address signal line bus for carrying an externally-generated digital code defining a column address; a digital code transformation circuit for generating an internal digital code based on the externally-generated digital code; and column address decoding and column selection circuits for receiving the internal digital code and, based thereon, selecting a column packet and a number of columns of memory cells equal to the selected number of memory cells; the generation of the internal digital code such that the columns of memory cells selected are a maximum distance from one another within the selected column packet.
11. A memory according to claim 7 wherein the selected number of said memory cells is equal to 2 n ; wherein the number of columns of memory cells in each column packet is equal to 2 m ; wherein said column selection circuit is such that, within each column packet, columns of memory cells containing memory cells written by said write circuit are distributed every 2 (m n) columns of the column packet.
12. A method of writing a memory comprising at least one array of memory cells arranged in a plurality of rows and a plurality of columns, a row selection circuit for selecting a row, a column selection circuit for selecting a column, a write circuit for simultaneously writing a selected number of said memory cells, a plurality of doped semiconductor regions subdividing memory cells into a plurality of subsets of memory cells that can each be individually erased, and a plurality of column packets that each contains a number of columns of memory cells less that than the selected number of memory cells, the method comprising: selecting a row; selecting a column packet; and for the selected column packet, selecting a number of columns, the columns containing memory cells that are written simultaneously by the write circuit such that the selected columns are distributed among the columns of the column packet to be at a maximum distance from each other within each column packet.
13. A method according to claim 12 wherein the number of columns is equal to the selected number of memory cells.
14. A method according to claim 12 wherein the selected number of memory cells is equal to 2 n ; wherein the number of columns of memory cells in each column packet is equal to 2 m ; wherein the column selection circuit is such that, within each column packet, columns of memory cells containing memory cells written by the write circuit are distributed every 2 (m n) columns of the column packet.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 24, 2002
September 9, 2003
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.